1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * The topology here is configurable; it can be a hierachical (default 31 * one) or a 2D torus or a 2D torus with half switches killed. I think 32 * all input port has a one-input-one-output switch connected just to 33 * control and bandwidth, since we don't control bandwidth on input 34 * ports. Basically, the class has a vector of nodes and edges. First 35 * 2*m_nodes elements in the node vector are input and output 36 * ports. Edges are represented in two vectors of src and dest 37 * nodes. All edges have latency. 38 */ 39
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40#ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
41#define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
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40#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__ 41#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__ |
42 43#include <iostream> 44#include <string> 45#include <vector> 46 47#include "mem/protocol/LinkDirection.hh" 48#include "mem/ruby/common/TypeDefines.hh"
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49#include "mem/ruby/network/BasicRouter.hh"
50#include "params/Topology.hh"
51#include "sim/sim_object.hh"
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49#include "mem/ruby/network/BasicLink.hh" |
50 51class NetDest; 52class Network; 53 54typedef std::vector<std::vector<int> > Matrix; 55 56struct LinkEntry 57{ 58 BasicLink *link; 59 LinkDirection direction; 60}; 61 62typedef std::map<std::pair<int, int>, LinkEntry> LinkMap; 63
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66class Topology : public SimObject
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64class Topology |
65{ 66 public:
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69 typedef TopologyParams Params;
70 Topology(const Params *p);
71 virtual ~Topology() {}
72 const Params *params() const { return (const Params *)_params; }
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67 Topology(uint32_t num_routers, std::vector<BasicExtLink *> ext_links, 68 std::vector<BasicIntLink *> int_links); |
69
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74 void init();
75 int numSwitches() const { return m_number_of_switches; }
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70 uint32_t numSwitches() const { return m_number_of_switches; } |
71 void createLinks(Network *net, bool isReconfiguration);
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77
78 void initNetworkPtr(Network* net_ptr);
79
80 const std::string getName() { return m_name; }
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72 void print(std::ostream& out) const { out << "[Topology]"; } 73 74 protected: 75 void addLink(SwitchID src, SwitchID dest, BasicLink* link, 76 LinkDirection dir); 77 void makeLink(Network *net, SwitchID src, SwitchID dest, 78 const NetDest& routing_table_entry, 79 bool isReconfiguration); 80
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90 std::string getDesignStr();
91 // Private copy constructor and assignment operator
92 Topology(const Topology& obj);
93 Topology& operator=(const Topology& obj);
94
95 std::string m_name;
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81 NodeID m_nodes;
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97 int m_number_of_switches;
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82 uint32_t m_number_of_switches; |
83 84 std::vector<BasicExtLink*> m_ext_link_vector; 85 std::vector<BasicIntLink*> m_int_link_vector; 86 87 Matrix m_component_latencies; 88 Matrix m_component_inter_switches; 89 90 LinkMap m_link_map;
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106 std::vector<BasicRouter*> m_router_vector;
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91}; 92 93inline std::ostream& 94operator<<(std::ostream& out, const Topology& obj) 95{ 96 obj.print(out); 97 out << std::flush; 98 return out; 99} 100
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117#endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
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101#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__ |
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