1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * The topology here is configurable; it can be a hierachical (default 31 * one) or a 2D torus or a 2D torus with half switches killed. I think 32 * all input port has a one-input-one-output switch connected just to 33 * control and bandwidth, since we don't control bandwidth on input 34 * ports. Basically, the class has a vector of nodes and edges. First 35 * 2*m_nodes elements in the node vector are input and output 36 * ports. Edges are represented in two vectors of src and dest 37 * nodes. All edges have latency. 38 */ 39 40#ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__ 41#define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__ 42 43#include <iostream> 44#include <string> 45#include <vector> 46
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47#include "mem/protocol/LinkDirection.hh" |
48#include "mem/ruby/common/Global.hh" 49#include "mem/ruby/system/NodeID.hh"
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49#include "params/ExtLink.hh"
50#include "params/IntLink.hh"
51#include "params/Link.hh"
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50#include "params/Topology.hh" 51#include "sim/sim_object.hh" 52
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55class Network;
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53class NetDest;
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54class Network; |
55 56typedef std::vector<std::vector<int> > Matrix; 57
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60class Link : public SimObject
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58struct LinkEntry |
59{
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62 public:
63 typedef LinkParams Params;
64 Link(const Params *p) : SimObject(p) {}
65 const Params *params() const { return (const Params *)_params; }
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60 BasicLink *link; 61 LinkDirection direction; |
62}; 63
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68class ExtLink : public Link
69{
70 public:
71 typedef ExtLinkParams Params;
72 ExtLink(const Params *p) : Link(p) {}
73 const Params *params() const { return (const Params *)_params; }
74};
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64typedef std::map<std::pair<int, int>, LinkEntry> LinkMap; |
65
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76class IntLink : public Link
77{
78 public:
79 typedef IntLinkParams Params;
80 IntLink(const Params *p) : Link(p) {}
81 const Params *params() const { return (const Params *)_params; }
82};
83
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66class Topology : public SimObject 67{ 68 public: 69 typedef TopologyParams Params; 70 Topology(const Params *p); 71 virtual ~Topology() {} 72 const Params *params() const { return (const Params *)_params; } 73
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74 void init(); |
75 int numSwitches() const { return m_number_of_switches; } 76 void createLinks(Network *net, bool isReconfiguration); 77 78 void initNetworkPtr(Network* net_ptr); 79 80 const std::string getName() { return m_name; } 81 void printStats(std::ostream& out) const; 82 void clearStats(); 83 void printConfig(std::ostream& out) const; 84 void print(std::ostream& out) const { out << "[Topology]"; } 85 86 protected:
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104 SwitchID newSwitchID();
105 void addLink(SwitchID src, SwitchID dest, int link_latency);
106 void addLink(SwitchID src, SwitchID dest, int link_latency,
107 int bw_multiplier);
108 void addLink(SwitchID src, SwitchID dest, int link_latency,
109 int bw_multiplier, int link_weight);
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87 void addLink(SwitchID src, SwitchID dest, BasicLink* link, 88 LinkDirection dir); |
89 void makeLink(Network *net, SwitchID src, SwitchID dest,
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111 const NetDest& routing_table_entry, int link_latency, int weight,
112 int bw_multiplier, bool isReconfiguration);
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90 const NetDest& routing_table_entry, 91 bool isReconfiguration); |
92
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114 //void makeSwitchesPerChip(std::vector<std::vector<SwitchID > > &nodePairs,
115 // std::vector<int> &latencies, std::vector<int> &bw_multis,
116 // int numberOfChips);
117
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93 std::string getDesignStr(); 94 // Private copy constructor and assignment operator 95 Topology(const Topology& obj); 96 Topology& operator=(const Topology& obj); 97 98 std::string m_name; 99 bool m_print_config; 100 NodeID m_nodes; 101 int m_number_of_switches; 102 103 std::vector<AbstractController*> m_controller_vector;
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104 std::vector<BasicExtLink*> m_ext_link_vector; 105 std::vector<BasicIntLink*> m_int_link_vector; |
106
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130 std::vector<SwitchID> m_links_src_vector;
131 std::vector<SwitchID> m_links_dest_vector;
132 std::vector<int> m_links_latency_vector;
133 std::vector<int> m_links_weight_vector;
134 std::vector<int> m_bw_multiplier_vector;
135
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107 Matrix m_component_latencies; 108 Matrix m_component_inter_switches;
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109 110 LinkMap m_link_map; 111 std::vector<BasicRouter*> m_router_vector; |
112}; 113 114inline std::ostream& 115operator<<(std::ostream& out, const Topology& obj) 116{ 117 obj.print(out); 118 out << std::flush; 119 return out; 120} 121 122#endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
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