1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The topology here is configurable; it can be a hierachical (default
31 * one) or a 2D torus or a 2D torus with half switches killed. I think
32 * all input port has a one-input-one-output switch connected just to
33 * control and bandwidth, since we don't control bandwidth on input
34 * ports. Basically, the class has a vector of nodes and edges. First
35 * 2*m_nodes elements in the node vector are input and output
36 * ports. Edges are represented in two vectors of src and dest
37 * nodes. All edges have latency.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
41#define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/ruby/common/TypeDefines.hh"
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The topology here is configurable; it can be a hierachical (default
31 * one) or a 2D torus or a 2D torus with half switches killed. I think
32 * all input port has a one-input-one-output switch connected just to
33 * control and bandwidth, since we don't control bandwidth on input
34 * ports. Basically, the class has a vector of nodes and edges. First
35 * 2*m_nodes elements in the node vector are input and output
36 * ports. Edges are represented in two vectors of src and dest
37 * nodes. All edges have latency.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
41#define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/ruby/common/TypeDefines.hh"
|
49#include "params/Topology.hh"
50#include "sim/sim_object.hh"
51
52class NetDest;
53class Network;
54
55typedef std::vector<std::vector<int> > Matrix;
56
57struct LinkEntry
58{
59 BasicLink *link;
60 LinkDirection direction;
61};
62
63typedef std::map<std::pair<int, int>, LinkEntry> LinkMap;
64
65class Topology : public SimObject
66{
67 public:
68 typedef TopologyParams Params;
69 Topology(const Params *p);
70 virtual ~Topology() {}
71 const Params *params() const { return (const Params *)_params; }
72
73 void init();
74 int numSwitches() const { return m_number_of_switches; }
75 void createLinks(Network *net, bool isReconfiguration);
76
77 void initNetworkPtr(Network* net_ptr);
78
79 const std::string getName() { return m_name; }
80 void printStats(std::ostream& out) const;
81 void clearStats();
82 void print(std::ostream& out) const { out << "[Topology]"; }
83
84 protected:
85 void addLink(SwitchID src, SwitchID dest, BasicLink* link,
86 LinkDirection dir);
87 void makeLink(Network *net, SwitchID src, SwitchID dest,
88 const NetDest& routing_table_entry,
89 bool isReconfiguration);
90
91 std::string getDesignStr();
92 // Private copy constructor and assignment operator
93 Topology(const Topology& obj);
94 Topology& operator=(const Topology& obj);
95
96 std::string m_name;
97 bool m_print_config;
98 NodeID m_nodes;
99 int m_number_of_switches;
100
101 std::vector<AbstractController*> m_controller_vector;
102 std::vector<BasicExtLink*> m_ext_link_vector;
103 std::vector<BasicIntLink*> m_int_link_vector;
104
105 Matrix m_component_latencies;
106 Matrix m_component_inter_switches;
107
108 LinkMap m_link_map;
109 std::vector<BasicRouter*> m_router_vector;
110};
111
112inline std::ostream&
113operator<<(std::ostream& out, const Topology& obj)
114{
115 obj.print(out);
116 out << std::flush;
117 return out;
118}
119
120#endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
| 50#include "params/Topology.hh"
51#include "sim/sim_object.hh"
52
53class NetDest;
54class Network;
55
56typedef std::vector<std::vector<int> > Matrix;
57
58struct LinkEntry
59{
60 BasicLink *link;
61 LinkDirection direction;
62};
63
64typedef std::map<std::pair<int, int>, LinkEntry> LinkMap;
65
66class Topology : public SimObject
67{
68 public:
69 typedef TopologyParams Params;
70 Topology(const Params *p);
71 virtual ~Topology() {}
72 const Params *params() const { return (const Params *)_params; }
73
74 void init();
75 int numSwitches() const { return m_number_of_switches; }
76 void createLinks(Network *net, bool isReconfiguration);
77
78 void initNetworkPtr(Network* net_ptr);
79
80 const std::string getName() { return m_name; }
81 void printStats(std::ostream& out) const;
82 void clearStats();
83 void print(std::ostream& out) const { out << "[Topology]"; }
84
85 protected:
86 void addLink(SwitchID src, SwitchID dest, BasicLink* link,
87 LinkDirection dir);
88 void makeLink(Network *net, SwitchID src, SwitchID dest,
89 const NetDest& routing_table_entry,
90 bool isReconfiguration);
91
92 std::string getDesignStr();
93 // Private copy constructor and assignment operator
94 Topology(const Topology& obj);
95 Topology& operator=(const Topology& obj);
96
97 std::string m_name;
98 bool m_print_config;
99 NodeID m_nodes;
100 int m_number_of_switches;
101
102 std::vector<AbstractController*> m_controller_vector;
103 std::vector<BasicExtLink*> m_ext_link_vector;
104 std::vector<BasicIntLink*> m_int_link_vector;
105
106 Matrix m_component_latencies;
107 Matrix m_component_inter_switches;
108
109 LinkMap m_link_map;
110 std::vector<BasicRouter*> m_router_vector;
111};
112
113inline std::ostream&
114operator<<(std::ostream& out, const Topology& obj)
115{
116 obj.print(out);
117 out << std::flush;
118 return out;
119}
120
121#endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
|