1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The topology here is configurable; it can be a hierachical (default
31 * one) or a 2D torus or a 2D torus with half switches killed. I think
32 * all input port has a one-input-one-output switch connected just to
33 * control and bandwidth, since we don't control bandwidth on input
34 * ports. Basically, the class has a vector of nodes and edges. First
35 * 2*m_nodes elements in the node vector are input and output
36 * ports. Edges are represented in two vectors of src and dest
37 * nodes. All edges have latency.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__
41#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/ruby/common/TypeDefines.hh"
49#include "mem/ruby/network/BasicLink.hh"
50
51class NetDest;
52class Network;
53
54typedef std::vector<std::vector<int> > Matrix;
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The topology here is configurable; it can be a hierachical (default
31 * one) or a 2D torus or a 2D torus with half switches killed. I think
32 * all input port has a one-input-one-output switch connected just to
33 * control and bandwidth, since we don't control bandwidth on input
34 * ports. Basically, the class has a vector of nodes and edges. First
35 * 2*m_nodes elements in the node vector are input and output
36 * ports. Edges are represented in two vectors of src and dest
37 * nodes. All edges have latency.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__
41#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
42
43#include <iostream>
44#include <string>
45#include <vector>
46
47#include "mem/protocol/LinkDirection.hh"
48#include "mem/ruby/common/TypeDefines.hh"
49#include "mem/ruby/network/BasicLink.hh"
50
51class NetDest;
52class Network;
53
54typedef std::vector<std::vector<int> > Matrix;
|
| 55typedef std::string PortDirection;
|
55
56struct LinkEntry
57{
58 BasicLink *link;
59 LinkDirection direction;
| 56
57struct LinkEntry
58{
59 BasicLink *link;
60 LinkDirection direction;
|
| 61 PortDirection src_outport_dirn;
62 PortDirection dst_inport_dirn;
|
60};
61
62typedef std::map<std::pair<SwitchID, SwitchID>, LinkEntry> LinkMap;
63
64class Topology
65{
66 public:
67 Topology(uint32_t num_routers, const std::vector<BasicExtLink *> &ext_links,
68 const std::vector<BasicIntLink *> &int_links);
69
70 uint32_t numSwitches() const { return m_number_of_switches; }
71 void createLinks(Network *net);
72 void print(std::ostream& out) const { out << "[Topology]"; }
73
74 private:
| 63};
64
65typedef std::map<std::pair<SwitchID, SwitchID>, LinkEntry> LinkMap;
66
67class Topology
68{
69 public:
70 Topology(uint32_t num_routers, const std::vector<BasicExtLink *> &ext_links,
71 const std::vector<BasicIntLink *> &int_links);
72
73 uint32_t numSwitches() const { return m_number_of_switches; }
74 void createLinks(Network *net);
75 void print(std::ostream& out) const { out << "[Topology]"; }
76
77 private:
|
75 void addLink(SwitchID src, SwitchID dest, BasicLink* link);
| 78 void addLink(SwitchID src, SwitchID dest, BasicLink* link,
79 PortDirection src_outport_dirn = "",
80 PortDirection dest_inport_dirn = "");
|
76 void makeLink(Network *net, SwitchID src, SwitchID dest,
77 const NetDest& routing_table_entry);
78
79 // Helper functions based on chapter 29 of Cormen et al.
80 void extend_shortest_path(Matrix ¤t_dist, Matrix &latencies,
81 Matrix &inter_switches);
82
83 std::vector<std::vector<int>> shortest_path(const Matrix &weights,
84 Matrix &latencies, Matrix &inter_switches);
85
86 bool link_is_shortest_path_to_node(SwitchID src, SwitchID next,
87 SwitchID final, const Matrix &weights, const Matrix &dist);
88
89 NetDest shortest_path_to_node(SwitchID src, SwitchID next,
90 const Matrix &weights, const Matrix &dist);
91
92 const uint32_t m_nodes;
93 const uint32_t m_number_of_switches;
94
95 std::vector<BasicExtLink*> m_ext_link_vector;
96 std::vector<BasicIntLink*> m_int_link_vector;
97
98 LinkMap m_link_map;
99};
100
101inline std::ostream&
102operator<<(std::ostream& out, const Topology& obj)
103{
104 obj.print(out);
105 out << std::flush;
106 return out;
107}
108
109#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__
| 81 void makeLink(Network *net, SwitchID src, SwitchID dest,
82 const NetDest& routing_table_entry);
83
84 // Helper functions based on chapter 29 of Cormen et al.
85 void extend_shortest_path(Matrix ¤t_dist, Matrix &latencies,
86 Matrix &inter_switches);
87
88 std::vector<std::vector<int>> shortest_path(const Matrix &weights,
89 Matrix &latencies, Matrix &inter_switches);
90
91 bool link_is_shortest_path_to_node(SwitchID src, SwitchID next,
92 SwitchID final, const Matrix &weights, const Matrix &dist);
93
94 NetDest shortest_path_to_node(SwitchID src, SwitchID next,
95 const Matrix &weights, const Matrix &dist);
96
97 const uint32_t m_nodes;
98 const uint32_t m_number_of_switches;
99
100 std::vector<BasicExtLink*> m_ext_link_vector;
101 std::vector<BasicIntLink*> m_int_link_vector;
102
103 LinkMap m_link_map;
104};
105
106inline std::ostream&
107operator<<(std::ostream& out, const Topology& obj)
108{
109 obj.print(out);
110 out << std::flush;
111 return out;
112}
113
114#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__
|