1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <cassert> 30 31#include "debug/RubyNetwork.hh" 32#include "mem/protocol/MachineType.hh" 33#include "mem/protocol/Protocol.hh" 34#include "mem/protocol/TopologyType.hh" 35#include "mem/ruby/common/NetDest.hh"
| 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <cassert> 30 31#include "debug/RubyNetwork.hh" 32#include "mem/protocol/MachineType.hh" 33#include "mem/protocol/Protocol.hh" 34#include "mem/protocol/TopologyType.hh" 35#include "mem/ruby/common/NetDest.hh"
|
| 36#include "mem/ruby/network/BasicLink.hh" 37#include "mem/ruby/network/BasicRouter.hh"
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36#include "mem/ruby/network/Network.hh" 37#include "mem/ruby/network/Topology.hh" 38#include "mem/ruby/slicc_interface/AbstractController.hh" 39#include "mem/ruby/system/System.hh" 40 41using namespace std; 42 43const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
| 38#include "mem/ruby/network/Network.hh" 39#include "mem/ruby/network/Topology.hh" 40#include "mem/ruby/slicc_interface/AbstractController.hh" 41#include "mem/ruby/system/System.hh" 42 43using namespace std; 44 45const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
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44const int DEFAULT_BW_MULTIPLIER = 1; // Just to be consistent with above :)
| |
45
| 46
|
| 47class BasicRouter; 48
|
46// Note: In this file, we use the first 2*m_nodes SwitchIDs to 47// represent the input and output endpoint links. These really are 48// not 'switches', as they will not have a Switch object allocated for 49// them. The first m_nodes SwitchIDs are the links into the network, 50// the second m_nodes set of SwitchIDs represent the the output queues 51// of the network. 52 53// Helper functions based on chapter 29 of Cormen et al. 54void extend_shortest_path(Matrix& current_dist, Matrix& latencies, 55 Matrix& inter_switches); 56Matrix shortest_path(const Matrix& weights, Matrix& latencies, 57 Matrix& inter_switches); 58bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, 59 SwitchID final, const Matrix& weights, const Matrix& dist); 60NetDest shortest_path_to_node(SwitchID src, SwitchID next, 61 const Matrix& weights, const Matrix& dist); 62 63Topology::Topology(const Params *p) 64 : SimObject(p) 65{ 66 m_print_config = p->print_config;
| 49// Note: In this file, we use the first 2*m_nodes SwitchIDs to 50// represent the input and output endpoint links. These really are 51// not 'switches', as they will not have a Switch object allocated for 52// them. The first m_nodes SwitchIDs are the links into the network, 53// the second m_nodes set of SwitchIDs represent the the output queues 54// of the network. 55 56// Helper functions based on chapter 29 of Cormen et al. 57void extend_shortest_path(Matrix& current_dist, Matrix& latencies, 58 Matrix& inter_switches); 59Matrix shortest_path(const Matrix& weights, Matrix& latencies, 60 Matrix& inter_switches); 61bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, 62 SwitchID final, const Matrix& weights, const Matrix& dist); 63NetDest shortest_path_to_node(SwitchID src, SwitchID next, 64 const Matrix& weights, const Matrix& dist); 65 66Topology::Topology(const Params *p) 67 : SimObject(p) 68{ 69 m_print_config = p->print_config;
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67 m_number_of_switches = p->num_int_nodes;
| 70 m_number_of_switches = p->routers.size(); 71
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68 // initialize component latencies record 69 m_component_latencies.resize(0); 70 m_component_inter_switches.resize(0); 71 72 // Total nodes/controllers in network 73 // Must make sure this is called after the State Machine constructors 74 m_nodes = MachineType_base_number(MachineType_NUM); 75 assert(m_nodes > 1); 76 77 if (m_nodes != params()->ext_links.size() && 78 m_nodes != params()->ext_links.size()) { 79 fatal("m_nodes (%d) != ext_links vector length (%d)\n",
| 72 // initialize component latencies record 73 m_component_latencies.resize(0); 74 m_component_inter_switches.resize(0); 75 76 // Total nodes/controllers in network 77 // Must make sure this is called after the State Machine constructors 78 m_nodes = MachineType_base_number(MachineType_NUM); 79 assert(m_nodes > 1); 80 81 if (m_nodes != params()->ext_links.size() && 82 m_nodes != params()->ext_links.size()) { 83 fatal("m_nodes (%d) != ext_links vector length (%d)\n",
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80 m_nodes != params()->ext_links.size());
| 84 m_nodes != params()->ext_links.size());
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81 } 82
| 85 } 86
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83 // First create the links between the endpoints (i.e. controllers) 84 // and the network. 85 for (vector<ExtLink*>::const_iterator i = params()->ext_links.begin();
| 87 // analyze both the internal and external links, create data structures 88 // Note that the python created links are bi-directional, but that the 89 // topology and networks utilize uni-directional links. Thus each 90 // BasicLink is converted to two calls to add link, on for each direction 91 for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
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86 i != params()->ext_links.end(); ++i) {
| 92 i != params()->ext_links.end(); ++i) {
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87 const ExtLinkParams *p = (*i)->params(); 88 AbstractController *c = p->ext_node;
| 93 BasicExtLink *ext_link = (*i); 94 AbstractController *abs_cntrl = ext_link->params()->ext_node; 95 BasicRouter *router = ext_link->params()->int_node;
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89
| 96
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90 // Store the controller pointers for later 91 m_controller_vector.push_back(c);
| 97 // Store the controller and ExtLink pointers for later 98 m_controller_vector.push_back(abs_cntrl); 99 m_ext_link_vector.push_back(ext_link);
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92
| 100
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93 int ext_idx1 = 94 MachineType_base_number(c->getMachineType()) + c->getVersion();
| 101 int ext_idx1 = abs_cntrl->params()->cntrl_id;
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95 int ext_idx2 = ext_idx1 + m_nodes;
| 102 int ext_idx2 = ext_idx1 + m_nodes;
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96 int int_idx = p->int_node + 2*m_nodes;
| 103 int int_idx = router->params()->router_id + 2*m_nodes;
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97
| 104
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98 // create the links in both directions 99 addLink(ext_idx1, int_idx, p->latency, p->bw_multiplier, p->weight); 100 addLink(int_idx, ext_idx2, p->latency, p->bw_multiplier, p->weight);
| 105 // create the internal uni-directional links in both directions 106 // the first direction is marked: In 107 addLink(ext_idx1, int_idx, ext_link, LinkDirection_In); 108 // the first direction is marked: Out 109 addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out);
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101 } 102
| 110 } 111
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103 for (vector::const_iterator i = params()->int_links.begin();
| 112 for (vector<BasicIntLink*>::const_iterator i = params()->int_links.begin();
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104 i != params()->int_links.end(); ++i) {
| 113 i != params()->int_links.end(); ++i) {
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105 const IntLinkParams *p = (*i)->params(); 106 int a = p->node_a + 2*m_nodes; 107 int b = p->node_b + 2*m_nodes;
| 114 BasicIntLink *int_link = (*i); 115 BasicRouter *router_a = int_link->params()->node_a; 116 BasicRouter *router_b = int_link->params()->node_b;
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108
| 117
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109 // create the links in both directions 110 addLink(a, b, p->latency, p->bw_multiplier, p->weight); 111 addLink(b, a, p->latency, p->bw_multiplier, p->weight);
| 118 // Store the IntLink pointers for later 119 m_int_link_vector.push_back(int_link); 120 121 int a = router_a->params()->router_id + 2*m_nodes; 122 int b = router_b->params()->router_id + 2*m_nodes; 123 124 // create the internal uni-directional links in both directions 125 // the first direction is marked: In 126 addLink(a, b, int_link, LinkDirection_In); 127 // the second direction is marked: Out 128 addLink(b, a, int_link, LinkDirection_Out);
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112 } 113} 114
| 129 } 130} 131
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| 132void 133Topology::init() 134{ 135}
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115
| 136
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| 137
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116void 117Topology::initNetworkPtr(Network* net_ptr) 118{
| 138void 139Topology::initNetworkPtr(Network* net_ptr) 140{
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119 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 120 m_controller_vector[cntrl]->initNetworkPtr(net_ptr);
| 141 for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin(); 142 i != params()->ext_links.end(); ++i) { 143 BasicExtLink *ext_link = (*i); 144 AbstractController *abs_cntrl = ext_link->params()->ext_node; 145 abs_cntrl->initNetworkPtr(net_ptr);
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121 } 122} 123 124void 125Topology::createLinks(Network *net, bool isReconfiguration) 126{ 127 // Find maximum switchID 128 SwitchID max_switch_id = 0;
| 146 } 147} 148 149void 150Topology::createLinks(Network *net, bool isReconfiguration) 151{ 152 // Find maximum switchID 153 SwitchID max_switch_id = 0;
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129 for (int i = 0; i < m_links_src_vector.size(); i++) { 130 max_switch_id = max(max_switch_id, m_links_src_vector[i]); 131 max_switch_id = max(max_switch_id, m_links_dest_vector[i]);
| 154 for (LinkMap::const_iterator i = m_link_map.begin(); 155 i != m_link_map.end(); ++i) { 156 std::pair<int, int> src_dest = (*i).first; 157 max_switch_id = max(max_switch_id, src_dest.first); 158 max_switch_id = max(max_switch_id, src_dest.second);
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132 } 133
| 159 } 160
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134 // Initialize weight vector
| 161 // Initialize weight, latency, and inter switched vectors
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135 Matrix topology_weights;
| 162 Matrix topology_weights;
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136 Matrix topology_latency; 137 Matrix topology_bw_multis;
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138 int num_switches = max_switch_id+1; 139 topology_weights.resize(num_switches);
| 163 int num_switches = max_switch_id+1; 164 topology_weights.resize(num_switches);
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140 topology_latency.resize(num_switches); 141 topology_bw_multis.resize(num_switches); 142 143 // FIXME setting the size of a member variable here is a HACK!
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144 m_component_latencies.resize(num_switches);
| 165 m_component_latencies.resize(num_switches);
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145 146 // FIXME setting the size of a member variable here is a HACK!
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147 m_component_inter_switches.resize(num_switches); 148 149 for (int i = 0; i < topology_weights.size(); i++) { 150 topology_weights[i].resize(num_switches);
| 166 m_component_inter_switches.resize(num_switches); 167 168 for (int i = 0; i < topology_weights.size(); i++) { 169 topology_weights[i].resize(num_switches);
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151 topology_latency[i].resize(num_switches); 152 topology_bw_multis[i].resize(num_switches);
| |
153 m_component_latencies[i].resize(num_switches);
| 170 m_component_latencies[i].resize(num_switches);
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154 155 // FIXME setting the size of a member variable here is a HACK!
| |
156 m_component_inter_switches[i].resize(num_switches); 157 158 for (int j = 0; j < topology_weights[i].size(); j++) { 159 topology_weights[i][j] = INFINITE_LATENCY; 160 161 // initialize to invalid values
| 171 m_component_inter_switches[i].resize(num_switches); 172 173 for (int j = 0; j < topology_weights[i].size(); j++) { 174 topology_weights[i][j] = INFINITE_LATENCY; 175 176 // initialize to invalid values
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162 topology_latency[i][j] = -1; 163 topology_bw_multis[i][j] = -1;
| |
164 m_component_latencies[i][j] = -1; 165 166 // initially assume direct connections / no intermediate 167 // switches between components 168 m_component_inter_switches[i][j] = 0; 169 } 170 } 171 172 // Set identity weights to zero 173 for (int i = 0; i < topology_weights.size(); i++) { 174 topology_weights[i][i] = 0; 175 } 176 177 // Fill in the topology weights and bandwidth multipliers
| 177 m_component_latencies[i][j] = -1; 178 179 // initially assume direct connections / no intermediate 180 // switches between components 181 m_component_inter_switches[i][j] = 0; 182 } 183 } 184 185 // Set identity weights to zero 186 for (int i = 0; i < topology_weights.size(); i++) { 187 topology_weights[i][i] = 0; 188 } 189 190 // Fill in the topology weights and bandwidth multipliers
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178 for (int i = 0; i < m_links_src_vector.size(); i++) { 179 int src = m_links_src_vector[i]; 180 int dst = m_links_dest_vector[i]; 181 topology_weights[src][dst] = m_links_weight_vector[i]; 182 topology_latency[src][dst] = m_links_latency_vector[i]; 183 m_component_latencies[src][dst] = m_links_latency_vector[i]; 184 topology_bw_multis[src][dst] = m_bw_multiplier_vector[i];
| 191 for (LinkMap::const_iterator i = m_link_map.begin(); 192 i != m_link_map.end(); ++i) { 193 std::pair<int, int> src_dest = (*i).first; 194 BasicLink* link = (*i).second.link; 195 int src = src_dest.first; 196 int dst = src_dest.second; 197 m_component_latencies[src][dst] = link->m_latency; 198 topology_weights[src][dst] = link->m_weight;
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185 }
| 199 }
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186
| 200
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187 // Walk topology and hookup the links 188 Matrix dist = shortest_path(topology_weights, m_component_latencies, 189 m_component_inter_switches); 190 for (int i = 0; i < topology_weights.size(); i++) { 191 for (int j = 0; j < topology_weights[i].size(); j++) { 192 int weight = topology_weights[i][j];
| 201 // Walk topology and hookup the links 202 Matrix dist = shortest_path(topology_weights, m_component_latencies, 203 m_component_inter_switches); 204 for (int i = 0; i < topology_weights.size(); i++) { 205 for (int j = 0; j < topology_weights[i].size(); j++) { 206 int weight = topology_weights[i][j];
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193 int bw_multiplier = topology_bw_multis[i][j]; 194 int latency = topology_latency[i][j];
| |
195 if (weight > 0 && weight != INFINITE_LATENCY) { 196 NetDest destination_set = shortest_path_to_node(i, j,
| 207 if (weight > 0 && weight != INFINITE_LATENCY) { 208 NetDest destination_set = shortest_path_to_node(i, j,
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197 topology_weights, dist); 198 assert(latency != -1); 199 makeLink(net, i, j, destination_set, latency, weight, 200 bw_multiplier, isReconfiguration);
| 209 topology_weights, dist); 210 makeLink(net, i, j, destination_set, isReconfiguration);
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201 } 202 } 203 } 204} 205
| 211 } 212 } 213 } 214} 215
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206SwitchID 207Topology::newSwitchID() 208{ 209 m_number_of_switches++; 210 return m_number_of_switches-1+m_nodes+m_nodes; 211} 212
| |
213void
| 216void
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214Topology::addLink(SwitchID src, SwitchID dest, int link_latency)
| 217Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, 218 LinkDirection dir)
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215{
| 219{
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216 addLink(src, dest, link_latency, DEFAULT_BW_MULTIPLIER, link_latency); 217} 218 219void 220Topology::addLink(SwitchID src, SwitchID dest, int link_latency, 221 int bw_multiplier) 222{ 223 addLink(src, dest, link_latency, bw_multiplier, link_latency); 224} 225 226void 227Topology::addLink(SwitchID src, SwitchID dest, int link_latency, 228 int bw_multiplier, int link_weight) 229{
| |
230 assert(src <= m_number_of_switches+m_nodes+m_nodes); 231 assert(dest <= m_number_of_switches+m_nodes+m_nodes);
| 220 assert(src <= m_number_of_switches+m_nodes+m_nodes); 221 assert(dest <= m_number_of_switches+m_nodes+m_nodes);
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232 m_links_src_vector.push_back(src); 233 m_links_dest_vector.push_back(dest); 234 m_links_latency_vector.push_back(link_latency); 235 m_links_weight_vector.push_back(link_weight); 236 m_bw_multiplier_vector.push_back(bw_multiplier);
| 222 223 std::pair<int, int> src_dest_pair; 224 LinkEntry link_entry; 225 226 src_dest_pair.first = src; 227 src_dest_pair.second = dest; 228 link_entry.direction = dir; 229 link_entry.link = link; 230 m_link_map[src_dest_pair] = link_entry;
|
237} 238 239void 240Topology::makeLink(Network *net, SwitchID src, SwitchID dest,
| 231} 232 233void 234Topology::makeLink(Network *net, SwitchID src, SwitchID dest,
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241 const NetDest& routing_table_entry, int link_latency, int link_weight, 242 int bw_multiplier, bool isReconfiguration)
| 235 const NetDest& routing_table_entry, bool isReconfiguration)
|
243{ 244 // Make sure we're not trying to connect two end-point nodes 245 // directly together 246 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 247
| 236{ 237 // Make sure we're not trying to connect two end-point nodes 238 // directly together 239 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes); 240
|
| 241 std::pair<int, int> src_dest; 242 LinkEntry link_entry; 243
|
248 if (src < m_nodes) {
| 244 if (src < m_nodes) {
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249 net->makeInLink(src, dest-(2*m_nodes), routing_table_entry, 250 link_latency, bw_multiplier, isReconfiguration);
| 245 src_dest.first = src; 246 src_dest.second = dest; 247 link_entry = m_link_map[src_dest]; 248 net->makeInLink(src, dest - (2 * m_nodes), link_entry.link, 249 link_entry.direction, 250 routing_table_entry, 251 isReconfiguration);
|
251 } else if (dest < 2*m_nodes) { 252 assert(dest >= m_nodes);
| 252 } else if (dest < 2*m_nodes) { 253 assert(dest >= m_nodes);
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253 NodeID node = dest-m_nodes; 254 net->makeOutLink(src-(2*m_nodes), node, routing_table_entry, 255 link_latency, link_weight, bw_multiplier, isReconfiguration);
| 254 NodeID node = dest - m_nodes; 255 src_dest.first = src; 256 src_dest.second = dest; 257 link_entry = m_link_map[src_dest]; 258 net->makeOutLink(src - (2 * m_nodes), node, link_entry.link, 259 link_entry.direction, 260 routing_table_entry, 261 isReconfiguration);
|
256 } else {
| 262 } else {
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257 assert((src >= 2*m_nodes) && (dest >= 2*m_nodes)); 258 net->makeInternalLink(src-(2*m_nodes), dest-(2*m_nodes), 259 routing_table_entry, link_latency, link_weight, bw_multiplier, 260 isReconfiguration);
| 263 assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes)); 264 src_dest.first = src; 265 src_dest.second = dest; 266 link_entry = m_link_map[src_dest]; 267 net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes), 268 link_entry.link, link_entry.direction, 269 routing_table_entry, isReconfiguration);
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261 } 262} 263 264void 265Topology::printStats(std::ostream& out) const 266{ 267 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 268 m_controller_vector[cntrl]->printStats(out); 269 } 270} 271 272void 273Topology::clearStats() 274{ 275 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 276 m_controller_vector[cntrl]->clearStats(); 277 } 278} 279 280void 281Topology::printConfig(std::ostream& out) const 282{ 283 if (m_print_config == false) 284 return; 285 286 assert(m_component_latencies.size() > 0); 287 288 out << "--- Begin Topology Print ---" << endl 289 << endl 290 << "Topology print ONLY indicates the _NETWORK_ latency between two " 291 << "machines" << endl 292 << "It does NOT include the latency within the machines" << endl 293 << endl; 294 295 for (int m = 0; m < MachineType_NUM; m++) { 296 int i_end = MachineType_base_count((MachineType)m); 297 for (int i = 0; i < i_end; i++) { 298 MachineID cur_mach = {(MachineType)m, i}; 299 out << cur_mach << " Network Latencies" << endl; 300 for (int n = 0; n < MachineType_NUM; n++) { 301 int j_end = MachineType_base_count((MachineType)n); 302 for (int j = 0; j < j_end; j++) { 303 MachineID dest_mach = {(MachineType)n, j}; 304 if (cur_mach == dest_mach) 305 continue; 306 307 int src = MachineType_base_number((MachineType)m) + i; 308 int dst = MachineType_base_number(MachineType_NUM) + 309 MachineType_base_number((MachineType)n) + j; 310 int link_latency = m_component_latencies[src][dst]; 311 int intermediate_switches = 312 m_component_inter_switches[src][dst]; 313 314 // NOTE switches are assumed to have single 315 // cycle latency 316 out << " " << cur_mach << " -> " << dest_mach 317 << " net_lat: " 318 << link_latency + intermediate_switches << endl; 319 } 320 } 321 out << endl; 322 } 323 } 324 325 out << "--- End Topology Print ---" << endl; 326} 327 328// The following all-pairs shortest path algorithm is based on the 329// discussion from Cormen et al., Chapter 26.1. 330void 331extend_shortest_path(Matrix& current_dist, Matrix& latencies, 332 Matrix& inter_switches) 333{ 334 bool change = true; 335 int nodes = current_dist.size(); 336 337 while (change) { 338 change = false; 339 for (int i = 0; i < nodes; i++) { 340 for (int j = 0; j < nodes; j++) { 341 int minimum = current_dist[i][j]; 342 int previous_minimum = minimum; 343 int intermediate_switch = -1; 344 for (int k = 0; k < nodes; k++) { 345 minimum = min(minimum, 346 current_dist[i][k] + current_dist[k][j]); 347 if (previous_minimum != minimum) { 348 intermediate_switch = k; 349 inter_switches[i][j] = 350 inter_switches[i][k] + 351 inter_switches[k][j] + 1; 352 } 353 previous_minimum = minimum; 354 } 355 if (current_dist[i][j] != minimum) { 356 change = true; 357 current_dist[i][j] = minimum; 358 assert(intermediate_switch >= 0); 359 assert(intermediate_switch < latencies[i].size()); 360 latencies[i][j] = latencies[i][intermediate_switch] + 361 latencies[intermediate_switch][j]; 362 } 363 } 364 } 365 } 366} 367 368Matrix 369shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) 370{ 371 Matrix dist = weights; 372 extend_shortest_path(dist, latencies, inter_switches); 373 return dist; 374} 375 376bool 377link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, 378 const Matrix& weights, const Matrix& dist) 379{ 380 return weights[src][next] + dist[next][final] == dist[src][final]; 381} 382 383NetDest 384shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, 385 const Matrix& dist) 386{ 387 NetDest result; 388 int d = 0; 389 int machines; 390 int max_machines; 391 392 machines = MachineType_NUM; 393 max_machines = MachineType_base_number(MachineType_NUM); 394 395 for (int m = 0; m < machines; m++) { 396 for (int i = 0; i < MachineType_base_count((MachineType)m); i++) { 397 // we use "d+max_machines" below since the "destination" 398 // switches for the machines are numbered 399 // [MachineType_base_number(MachineType_NUM)... 400 // 2*MachineType_base_number(MachineType_NUM)-1] for the 401 // component network 402 if (link_is_shortest_path_to_node(src, next, d + max_machines, 403 weights, dist)) { 404 MachineID mach = {(MachineType)m, i}; 405 result.add(mach); 406 } 407 d++; 408 } 409 } 410 411 DPRINTF(RubyNetwork, "Returning shortest path\n" 412 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, " 413 "src: %d, next: %d, result: %s\n", 414 (src-(2*max_machines)), (next-(2*max_machines)), 415 src, next, result); 416 417 return result; 418} 419 420Topology * 421TopologyParams::create() 422{ 423 return new Topology(this); 424} 425
| 270 } 271} 272 273void 274Topology::printStats(std::ostream& out) const 275{ 276 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 277 m_controller_vector[cntrl]->printStats(out); 278 } 279} 280 281void 282Topology::clearStats() 283{ 284 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) { 285 m_controller_vector[cntrl]->clearStats(); 286 } 287} 288 289void 290Topology::printConfig(std::ostream& out) const 291{ 292 if (m_print_config == false) 293 return; 294 295 assert(m_component_latencies.size() > 0); 296 297 out << "--- Begin Topology Print ---" << endl 298 << endl 299 << "Topology print ONLY indicates the _NETWORK_ latency between two " 300 << "machines" << endl 301 << "It does NOT include the latency within the machines" << endl 302 << endl; 303 304 for (int m = 0; m < MachineType_NUM; m++) { 305 int i_end = MachineType_base_count((MachineType)m); 306 for (int i = 0; i < i_end; i++) { 307 MachineID cur_mach = {(MachineType)m, i}; 308 out << cur_mach << " Network Latencies" << endl; 309 for (int n = 0; n < MachineType_NUM; n++) { 310 int j_end = MachineType_base_count((MachineType)n); 311 for (int j = 0; j < j_end; j++) { 312 MachineID dest_mach = {(MachineType)n, j}; 313 if (cur_mach == dest_mach) 314 continue; 315 316 int src = MachineType_base_number((MachineType)m) + i; 317 int dst = MachineType_base_number(MachineType_NUM) + 318 MachineType_base_number((MachineType)n) + j; 319 int link_latency = m_component_latencies[src][dst]; 320 int intermediate_switches = 321 m_component_inter_switches[src][dst]; 322 323 // NOTE switches are assumed to have single 324 // cycle latency 325 out << " " << cur_mach << " -> " << dest_mach 326 << " net_lat: " 327 << link_latency + intermediate_switches << endl; 328 } 329 } 330 out << endl; 331 } 332 } 333 334 out << "--- End Topology Print ---" << endl; 335} 336 337// The following all-pairs shortest path algorithm is based on the 338// discussion from Cormen et al., Chapter 26.1. 339void 340extend_shortest_path(Matrix& current_dist, Matrix& latencies, 341 Matrix& inter_switches) 342{ 343 bool change = true; 344 int nodes = current_dist.size(); 345 346 while (change) { 347 change = false; 348 for (int i = 0; i < nodes; i++) { 349 for (int j = 0; j < nodes; j++) { 350 int minimum = current_dist[i][j]; 351 int previous_minimum = minimum; 352 int intermediate_switch = -1; 353 for (int k = 0; k < nodes; k++) { 354 minimum = min(minimum, 355 current_dist[i][k] + current_dist[k][j]); 356 if (previous_minimum != minimum) { 357 intermediate_switch = k; 358 inter_switches[i][j] = 359 inter_switches[i][k] + 360 inter_switches[k][j] + 1; 361 } 362 previous_minimum = minimum; 363 } 364 if (current_dist[i][j] != minimum) { 365 change = true; 366 current_dist[i][j] = minimum; 367 assert(intermediate_switch >= 0); 368 assert(intermediate_switch < latencies[i].size()); 369 latencies[i][j] = latencies[i][intermediate_switch] + 370 latencies[intermediate_switch][j]; 371 } 372 } 373 } 374 } 375} 376 377Matrix 378shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) 379{ 380 Matrix dist = weights; 381 extend_shortest_path(dist, latencies, inter_switches); 382 return dist; 383} 384 385bool 386link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, 387 const Matrix& weights, const Matrix& dist) 388{ 389 return weights[src][next] + dist[next][final] == dist[src][final]; 390} 391 392NetDest 393shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, 394 const Matrix& dist) 395{ 396 NetDest result; 397 int d = 0; 398 int machines; 399 int max_machines; 400 401 machines = MachineType_NUM; 402 max_machines = MachineType_base_number(MachineType_NUM); 403 404 for (int m = 0; m < machines; m++) { 405 for (int i = 0; i < MachineType_base_count((MachineType)m); i++) { 406 // we use "d+max_machines" below since the "destination" 407 // switches for the machines are numbered 408 // [MachineType_base_number(MachineType_NUM)... 409 // 2*MachineType_base_number(MachineType_NUM)-1] for the 410 // component network 411 if (link_is_shortest_path_to_node(src, next, d + max_machines, 412 weights, dist)) { 413 MachineID mach = {(MachineType)m, i}; 414 result.add(mach); 415 } 416 d++; 417 } 418 } 419 420 DPRINTF(RubyNetwork, "Returning shortest path\n" 421 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, " 422 "src: %d, next: %d, result: %s\n", 423 (src-(2*max_machines)), (next-(2*max_machines)), 424 src, next, result); 425 426 return result; 427} 428 429Topology * 430TopologyParams::create() 431{ 432 return new Topology(this); 433} 434
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426Link * 427LinkParams::create() 428{ 429 return new Link(this); 430} 431 432ExtLink * 433ExtLinkParams::create() 434{ 435 return new ExtLink(this); 436} 437 438IntLink * 439IntLinkParams::create() 440{ 441 return new IntLink(this); 442}
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