1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 19 unchanged lines hidden (view full) ---
28
29#include <cassert>
30
31#include "debug/RubyNetwork.hh"
32#include "mem/protocol/MachineType.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/protocol/TopologyType.hh"
35#include "mem/ruby/common/NetDest.hh"
36#include "mem/ruby/network/BasicLink.hh"
37#include "mem/ruby/network/BasicRouter.hh"
38#include "mem/ruby/network/Network.hh"
39#include "mem/ruby/network/Topology.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/System.hh"
42
43using namespace std;
44
45const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
46
47class BasicRouter;
48
49// Note: In this file, we use the first 2*m_nodes SwitchIDs to
50// represent the input and output endpoint links. These really are
51// not 'switches', as they will not have a Switch object allocated for
52// them. The first m_nodes SwitchIDs are the links into the network,
53// the second m_nodes set of SwitchIDs represent the the output queues
54// of the network.
55
56// Helper functions based on chapter 29 of Cormen et al.
--- 5 unchanged lines hidden (view full) ---
62 SwitchID final, const Matrix& weights, const Matrix& dist);
63NetDest shortest_path_to_node(SwitchID src, SwitchID next,
64 const Matrix& weights, const Matrix& dist);
65
66Topology::Topology(const Params *p)
67 : SimObject(p)
68{
69 m_print_config = p->print_config;
70 m_number_of_switches = p->routers.size();
71
72 // initialize component latencies record
73 m_component_latencies.resize(0);
74 m_component_inter_switches.resize(0);
75
76 // Total nodes/controllers in network
77 // Must make sure this is called after the State Machine constructors
78 m_nodes = MachineType_base_number(MachineType_NUM);
79 assert(m_nodes > 1);
80
81 if (m_nodes != params()->ext_links.size() &&
82 m_nodes != params()->ext_links.size()) {
83 fatal("m_nodes (%d) != ext_links vector length (%d)\n",
84 m_nodes != params()->ext_links.size());
85 }
86
87 // analyze both the internal and external links, create data structures
88 // Note that the python created links are bi-directional, but that the
89 // topology and networks utilize uni-directional links. Thus each
90 // BasicLink is converted to two calls to add link, on for each direction
91 for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
92 i != params()->ext_links.end(); ++i) {
93 BasicExtLink *ext_link = (*i);
94 AbstractController *abs_cntrl = ext_link->params()->ext_node;
95 BasicRouter *router = ext_link->params()->int_node;
96
97 // Store the controller and ExtLink pointers for later
98 m_controller_vector.push_back(abs_cntrl);
99 m_ext_link_vector.push_back(ext_link);
100
101 int ext_idx1 = abs_cntrl->params()->cntrl_id;
102 int ext_idx2 = ext_idx1 + m_nodes;
103 int int_idx = router->params()->router_id + 2*m_nodes;
104
105 // create the internal uni-directional links in both directions
106 // the first direction is marked: In
107 addLink(ext_idx1, int_idx, ext_link, LinkDirection_In);
108 // the first direction is marked: Out
109 addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out);
110 }
111
112 for (vector<BasicIntLink*>::const_iterator i = params()->int_links.begin();
113 i != params()->int_links.end(); ++i) {
114 BasicIntLink *int_link = (*i);
115 BasicRouter *router_a = int_link->params()->node_a;
116 BasicRouter *router_b = int_link->params()->node_b;
117
118 // Store the IntLink pointers for later
119 m_int_link_vector.push_back(int_link);
120
121 int a = router_a->params()->router_id + 2*m_nodes;
122 int b = router_b->params()->router_id + 2*m_nodes;
123
124 // create the internal uni-directional links in both directions
125 // the first direction is marked: In
126 addLink(a, b, int_link, LinkDirection_In);
127 // the second direction is marked: Out
128 addLink(b, a, int_link, LinkDirection_Out);
129 }
130}
131
132void
133Topology::init()
134{
135}
136
137
138void
139Topology::initNetworkPtr(Network* net_ptr)
140{
141 for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
142 i != params()->ext_links.end(); ++i) {
143 BasicExtLink *ext_link = (*i);
144 AbstractController *abs_cntrl = ext_link->params()->ext_node;
145 abs_cntrl->initNetworkPtr(net_ptr);
146 }
147}
148
149void
150Topology::createLinks(Network *net, bool isReconfiguration)
151{
152 // Find maximum switchID
153 SwitchID max_switch_id = 0;
154 for (LinkMap::const_iterator i = m_link_map.begin();
155 i != m_link_map.end(); ++i) {
156 std::pair<int, int> src_dest = (*i).first;
157 max_switch_id = max(max_switch_id, src_dest.first);
158 max_switch_id = max(max_switch_id, src_dest.second);
159 }
160
161 // Initialize weight, latency, and inter switched vectors
162 Matrix topology_weights;
163 int num_switches = max_switch_id+1;
164 topology_weights.resize(num_switches);
165 m_component_latencies.resize(num_switches);
166 m_component_inter_switches.resize(num_switches);
167
168 for (int i = 0; i < topology_weights.size(); i++) {
169 topology_weights[i].resize(num_switches);
170 m_component_latencies[i].resize(num_switches);
171 m_component_inter_switches[i].resize(num_switches);
172
173 for (int j = 0; j < topology_weights[i].size(); j++) {
174 topology_weights[i][j] = INFINITE_LATENCY;
175
176 // initialize to invalid values
177 m_component_latencies[i][j] = -1;
178
179 // initially assume direct connections / no intermediate
180 // switches between components
181 m_component_inter_switches[i][j] = 0;
182 }
183 }
184
185 // Set identity weights to zero
186 for (int i = 0; i < topology_weights.size(); i++) {
187 topology_weights[i][i] = 0;
188 }
189
190 // Fill in the topology weights and bandwidth multipliers
191 for (LinkMap::const_iterator i = m_link_map.begin();
192 i != m_link_map.end(); ++i) {
193 std::pair<int, int> src_dest = (*i).first;
194 BasicLink* link = (*i).second.link;
195 int src = src_dest.first;
196 int dst = src_dest.second;
197 m_component_latencies[src][dst] = link->m_latency;
198 topology_weights[src][dst] = link->m_weight;
199 }
200
201 // Walk topology and hookup the links
202 Matrix dist = shortest_path(topology_weights, m_component_latencies,
203 m_component_inter_switches);
204 for (int i = 0; i < topology_weights.size(); i++) {
205 for (int j = 0; j < topology_weights[i].size(); j++) {
206 int weight = topology_weights[i][j];
207 if (weight > 0 && weight != INFINITE_LATENCY) {
208 NetDest destination_set = shortest_path_to_node(i, j,
209 topology_weights, dist);
210 makeLink(net, i, j, destination_set, isReconfiguration);
211 }
212 }
213 }
214}
215
216void
217Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link,
218 LinkDirection dir)
219{
220 assert(src <= m_number_of_switches+m_nodes+m_nodes);
221 assert(dest <= m_number_of_switches+m_nodes+m_nodes);
222
223 std::pair<int, int> src_dest_pair;
224 LinkEntry link_entry;
225
226 src_dest_pair.first = src;
227 src_dest_pair.second = dest;
228 link_entry.direction = dir;
229 link_entry.link = link;
230 m_link_map[src_dest_pair] = link_entry;
231}
232
233void
234Topology::makeLink(Network *net, SwitchID src, SwitchID dest,
235 const NetDest& routing_table_entry, bool isReconfiguration)
236{
237 // Make sure we're not trying to connect two end-point nodes
238 // directly together
239 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes);
240
241 std::pair<int, int> src_dest;
242 LinkEntry link_entry;
243
244 if (src < m_nodes) {
245 src_dest.first = src;
246 src_dest.second = dest;
247 link_entry = m_link_map[src_dest];
248 net->makeInLink(src, dest - (2 * m_nodes), link_entry.link,
249 link_entry.direction,
250 routing_table_entry,
251 isReconfiguration);
252 } else if (dest < 2*m_nodes) {
253 assert(dest >= m_nodes);
254 NodeID node = dest - m_nodes;
255 src_dest.first = src;
256 src_dest.second = dest;
257 link_entry = m_link_map[src_dest];
258 net->makeOutLink(src - (2 * m_nodes), node, link_entry.link,
259 link_entry.direction,
260 routing_table_entry,
261 isReconfiguration);
262 } else {
263 assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes));
264 src_dest.first = src;
265 src_dest.second = dest;
266 link_entry = m_link_map[src_dest];
267 net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes),
268 link_entry.link, link_entry.direction,
269 routing_table_entry, isReconfiguration);
270 }
271}
272
273void
274Topology::printStats(std::ostream& out) const
275{
276 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) {
277 m_controller_vector[cntrl]->printStats(out);
--- 149 unchanged lines hidden (view full) ---
427}
428
429Topology *
430TopologyParams::create()
431{
432 return new Topology(this);
433}
434
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 19 unchanged lines hidden (view full) ---
28
29#include <cassert>
30
31#include "debug/RubyNetwork.hh"
32#include "mem/protocol/MachineType.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/protocol/TopologyType.hh"
35#include "mem/ruby/common/NetDest.hh"
36#include "mem/ruby/network/BasicLink.hh"
37#include "mem/ruby/network/BasicRouter.hh"
38#include "mem/ruby/network/Network.hh"
39#include "mem/ruby/network/Topology.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/System.hh"
42
43using namespace std;
44
45const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
46
47class BasicRouter;
48
49// Note: In this file, we use the first 2*m_nodes SwitchIDs to
50// represent the input and output endpoint links. These really are
51// not 'switches', as they will not have a Switch object allocated for
52// them. The first m_nodes SwitchIDs are the links into the network,
53// the second m_nodes set of SwitchIDs represent the the output queues
54// of the network.
55
56// Helper functions based on chapter 29 of Cormen et al.
--- 5 unchanged lines hidden (view full) ---
62 SwitchID final, const Matrix& weights, const Matrix& dist);
63NetDest shortest_path_to_node(SwitchID src, SwitchID next,
64 const Matrix& weights, const Matrix& dist);
65
66Topology::Topology(const Params *p)
67 : SimObject(p)
68{
69 m_print_config = p->print_config;
70 m_number_of_switches = p->routers.size();
71
72 // initialize component latencies record
73 m_component_latencies.resize(0);
74 m_component_inter_switches.resize(0);
75
76 // Total nodes/controllers in network
77 // Must make sure this is called after the State Machine constructors
78 m_nodes = MachineType_base_number(MachineType_NUM);
79 assert(m_nodes > 1);
80
81 if (m_nodes != params()->ext_links.size() &&
82 m_nodes != params()->ext_links.size()) {
83 fatal("m_nodes (%d) != ext_links vector length (%d)\n",
84 m_nodes != params()->ext_links.size());
85 }
86
87 // analyze both the internal and external links, create data structures
88 // Note that the python created links are bi-directional, but that the
89 // topology and networks utilize uni-directional links. Thus each
90 // BasicLink is converted to two calls to add link, on for each direction
91 for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
92 i != params()->ext_links.end(); ++i) {
93 BasicExtLink *ext_link = (*i);
94 AbstractController *abs_cntrl = ext_link->params()->ext_node;
95 BasicRouter *router = ext_link->params()->int_node;
96
97 // Store the controller and ExtLink pointers for later
98 m_controller_vector.push_back(abs_cntrl);
99 m_ext_link_vector.push_back(ext_link);
100
101 int ext_idx1 = abs_cntrl->params()->cntrl_id;
102 int ext_idx2 = ext_idx1 + m_nodes;
103 int int_idx = router->params()->router_id + 2*m_nodes;
104
105 // create the internal uni-directional links in both directions
106 // the first direction is marked: In
107 addLink(ext_idx1, int_idx, ext_link, LinkDirection_In);
108 // the first direction is marked: Out
109 addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out);
110 }
111
112 for (vector<BasicIntLink*>::const_iterator i = params()->int_links.begin();
113 i != params()->int_links.end(); ++i) {
114 BasicIntLink *int_link = (*i);
115 BasicRouter *router_a = int_link->params()->node_a;
116 BasicRouter *router_b = int_link->params()->node_b;
117
118 // Store the IntLink pointers for later
119 m_int_link_vector.push_back(int_link);
120
121 int a = router_a->params()->router_id + 2*m_nodes;
122 int b = router_b->params()->router_id + 2*m_nodes;
123
124 // create the internal uni-directional links in both directions
125 // the first direction is marked: In
126 addLink(a, b, int_link, LinkDirection_In);
127 // the second direction is marked: Out
128 addLink(b, a, int_link, LinkDirection_Out);
129 }
130}
131
132void
133Topology::init()
134{
135}
136
137
138void
139Topology::initNetworkPtr(Network* net_ptr)
140{
141 for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
142 i != params()->ext_links.end(); ++i) {
143 BasicExtLink *ext_link = (*i);
144 AbstractController *abs_cntrl = ext_link->params()->ext_node;
145 abs_cntrl->initNetworkPtr(net_ptr);
146 }
147}
148
149void
150Topology::createLinks(Network *net, bool isReconfiguration)
151{
152 // Find maximum switchID
153 SwitchID max_switch_id = 0;
154 for (LinkMap::const_iterator i = m_link_map.begin();
155 i != m_link_map.end(); ++i) {
156 std::pair<int, int> src_dest = (*i).first;
157 max_switch_id = max(max_switch_id, src_dest.first);
158 max_switch_id = max(max_switch_id, src_dest.second);
159 }
160
161 // Initialize weight, latency, and inter switched vectors
162 Matrix topology_weights;
163 int num_switches = max_switch_id+1;
164 topology_weights.resize(num_switches);
165 m_component_latencies.resize(num_switches);
166 m_component_inter_switches.resize(num_switches);
167
168 for (int i = 0; i < topology_weights.size(); i++) {
169 topology_weights[i].resize(num_switches);
170 m_component_latencies[i].resize(num_switches);
171 m_component_inter_switches[i].resize(num_switches);
172
173 for (int j = 0; j < topology_weights[i].size(); j++) {
174 topology_weights[i][j] = INFINITE_LATENCY;
175
176 // initialize to invalid values
177 m_component_latencies[i][j] = -1;
178
179 // initially assume direct connections / no intermediate
180 // switches between components
181 m_component_inter_switches[i][j] = 0;
182 }
183 }
184
185 // Set identity weights to zero
186 for (int i = 0; i < topology_weights.size(); i++) {
187 topology_weights[i][i] = 0;
188 }
189
190 // Fill in the topology weights and bandwidth multipliers
191 for (LinkMap::const_iterator i = m_link_map.begin();
192 i != m_link_map.end(); ++i) {
193 std::pair<int, int> src_dest = (*i).first;
194 BasicLink* link = (*i).second.link;
195 int src = src_dest.first;
196 int dst = src_dest.second;
197 m_component_latencies[src][dst] = link->m_latency;
198 topology_weights[src][dst] = link->m_weight;
199 }
200
201 // Walk topology and hookup the links
202 Matrix dist = shortest_path(topology_weights, m_component_latencies,
203 m_component_inter_switches);
204 for (int i = 0; i < topology_weights.size(); i++) {
205 for (int j = 0; j < topology_weights[i].size(); j++) {
206 int weight = topology_weights[i][j];
207 if (weight > 0 && weight != INFINITE_LATENCY) {
208 NetDest destination_set = shortest_path_to_node(i, j,
209 topology_weights, dist);
210 makeLink(net, i, j, destination_set, isReconfiguration);
211 }
212 }
213 }
214}
215
216void
217Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link,
218 LinkDirection dir)
219{
220 assert(src <= m_number_of_switches+m_nodes+m_nodes);
221 assert(dest <= m_number_of_switches+m_nodes+m_nodes);
222
223 std::pair<int, int> src_dest_pair;
224 LinkEntry link_entry;
225
226 src_dest_pair.first = src;
227 src_dest_pair.second = dest;
228 link_entry.direction = dir;
229 link_entry.link = link;
230 m_link_map[src_dest_pair] = link_entry;
231}
232
233void
234Topology::makeLink(Network *net, SwitchID src, SwitchID dest,
235 const NetDest& routing_table_entry, bool isReconfiguration)
236{
237 // Make sure we're not trying to connect two end-point nodes
238 // directly together
239 assert(src >= 2 * m_nodes || dest >= 2 * m_nodes);
240
241 std::pair<int, int> src_dest;
242 LinkEntry link_entry;
243
244 if (src < m_nodes) {
245 src_dest.first = src;
246 src_dest.second = dest;
247 link_entry = m_link_map[src_dest];
248 net->makeInLink(src, dest - (2 * m_nodes), link_entry.link,
249 link_entry.direction,
250 routing_table_entry,
251 isReconfiguration);
252 } else if (dest < 2*m_nodes) {
253 assert(dest >= m_nodes);
254 NodeID node = dest - m_nodes;
255 src_dest.first = src;
256 src_dest.second = dest;
257 link_entry = m_link_map[src_dest];
258 net->makeOutLink(src - (2 * m_nodes), node, link_entry.link,
259 link_entry.direction,
260 routing_table_entry,
261 isReconfiguration);
262 } else {
263 assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes));
264 src_dest.first = src;
265 src_dest.second = dest;
266 link_entry = m_link_map[src_dest];
267 net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes),
268 link_entry.link, link_entry.direction,
269 routing_table_entry, isReconfiguration);
270 }
271}
272
273void
274Topology::printStats(std::ostream& out) const
275{
276 for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) {
277 m_controller_vector[cntrl]->printStats(out);
--- 149 unchanged lines hidden (view full) ---
427}
428
429Topology *
430TopologyParams::create()
431{
432 return new Topology(this);
433}
434