1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/*
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30 * Network.hh
31 *
32 * Description: The Network class is the base class for classes that
33 * implement the interconnection network between components
34 * (processor/cache components and memory/directory components). The
35 * interconnection network as described here is not a physical
36 * network, but a programming concept used to implement all
37 * communication between components. Thus parts of this 'network'
38 * will model the on-chip connections between cache controllers and
39 * directory controllers as well as the links between chip and network
40 * switches.
41 *
42 * $Id$
43 * */
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30 * The Network class is the base class for classes that implement the 31 * interconnection network between components (processor/cache 32 * components and memory/directory components). The interconnection 33 * network as described here is not a physical network, but a 34 * programming concept used to implement all communication between 35 * components. Thus parts of this 'network' will model the on-chip 36 * connections between cache controllers and directory controllers as 37 * well as the links between chip and network switches. 38 */ |
39
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45#ifndef NETWORK_H
46#define NETWORK_H
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40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__ 41#define __MEM_RUBY_NETWORK_NETWORK_HH__ |
42
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43#include "mem/protocol/MessageSizeType.hh" |
44#include "mem/ruby/common/Global.hh" 45#include "mem/ruby/system/NodeID.hh"
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50#include "mem/protocol/MessageSizeType.hh"
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46#include "mem/ruby/system/System.hh"
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52#include "sim/sim_object.hh"
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47#include "params/RubyNetwork.hh"
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48#include "sim/sim_object.hh" |
49 50class NetDest; 51class MessageBuffer; 52class Throttle; 53class Topology; 54
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60class Network : public SimObject {
61public:
62 // Constructors
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55class Network : public SimObject 56{ 57 public: |
58 typedef RubyNetworkParams Params; 59 Network(const Params *p);
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65 virtual void init();
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60 virtual ~Network() {} |
61
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67 // Destructor
68 virtual ~Network() {}
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62 virtual void init(); |
63
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70 // Public Methods
71 int getBufferSize() { return m_buffer_size; }
72 int getNumberOfVirtualNetworks() { return m_virtual_networks; }
73 int getEndpointBandwidth() { return m_endpoint_bandwidth; }
74 bool getAdaptiveRouting() {return m_adaptive_routing; }
75 int getLinkLatency() { return m_link_latency; }
76 int MessageSizeType_to_int(MessageSizeType size_type);
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64 int getBufferSize() { return m_buffer_size; } 65 int getNumberOfVirtualNetworks() { return m_virtual_networks; } 66 int getEndpointBandwidth() { return m_endpoint_bandwidth; } 67 bool getAdaptiveRouting() {return m_adaptive_routing; } 68 int getLinkLatency() { return m_link_latency; } 69 int MessageSizeType_to_int(MessageSizeType size_type); |
70
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71 // returns the queue requested for the given component 72 virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered, 73 int netNumber) = 0; 74 virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered, 75 int netNumber) = 0; 76 virtual const Vector<Throttle*>* getThrottles(NodeID id) const; 77 virtual int getNumNodes() {return 1;} |
78
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79 // returns the queue requested for the given component
80 virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered, int netNumber) = 0;
81 virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int netNumber) = 0;
82 virtual const Vector<Throttle*>* getThrottles(NodeID id) const { return NULL; }
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79 virtual void makeOutLink(SwitchID src, NodeID dest, 80 const NetDest& routing_table_entry, int link_latency, int link_weight, 81 int bw_multiplier, bool isReconfiguration) = 0; 82 virtual void makeInLink(SwitchID src, NodeID dest, 83 const NetDest& routing_table_entry, int link_latency, 84 int bw_multiplier, bool isReconfiguration) = 0; 85 virtual void makeInternalLink(SwitchID src, NodeID dest, 86 const NetDest& routing_table_entry, int link_latency, int link_weight, 87 int bw_multiplier, bool isReconfiguration) = 0; |
88
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84 virtual int getNumNodes() {return 1;}
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89 virtual void reset() = 0; |
90
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86 virtual void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) = 0;
87 virtual void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration) = 0;
88 virtual void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) = 0;
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91 virtual void printStats(ostream& out) const = 0; 92 virtual void clearStats() = 0; 93 virtual void printConfig(ostream& out) const = 0; 94 virtual void print(ostream& out) const = 0; |
95
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90 virtual void reset() = 0;
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96 protected: 97 // Private copy constructor and assignment operator 98 Network(const Network& obj); 99 Network& operator=(const Network& obj); |
100
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92 virtual void printStats(ostream& out) const = 0;
93 virtual void clearStats() = 0;
94 virtual void printConfig(ostream& out) const = 0;
95 virtual void print(ostream& out) const = 0;
96
97protected:
98
99 // Private Methods
100 // Private copy constructor and assignment operator
101 Network(const Network& obj);
102 Network& operator=(const Network& obj);
103
104 // Data Members (m_ prefix)
105protected:
106 const string m_name;
107 int m_nodes;
108 int m_virtual_networks;
109 int m_buffer_size;
110 int m_endpoint_bandwidth;
111 Topology* m_topology_ptr;
112 bool m_adaptive_routing;
113 int m_link_latency;
114 int m_control_msg_size;
115 int m_data_msg_size;
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101 protected: 102 const string m_name; 103 int m_nodes; 104 int m_virtual_networks; 105 int m_buffer_size; 106 int m_endpoint_bandwidth; 107 Topology* m_topology_ptr; 108 bool m_adaptive_routing; 109 int m_link_latency; 110 int m_control_msg_size; 111 int m_data_msg_size; |
112}; 113
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118// Output operator declaration
119ostream& operator<<(ostream& out, const Network& obj);
120
121// ******************* Definitions *******************
122
123// Output operator definition
124extern inline
125ostream& operator<<(ostream& out, const Network& obj)
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114inline ostream& 115operator<<(ostream& out, const Network& obj) |
116{
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127 obj.print(out);
128 out << flush;
129 return out;
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117 obj.print(out); 118 out << flush; 119 return out; |
120} 121
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132#endif //NETWORK_H
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122#endif // __MEM_RUBY_NETWORK_NETWORK_HH__ |
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