1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The Network class is the base class for classes that implement the
31 * interconnection network between components (processor/cache
32 * components and memory/directory components). The interconnection
33 * network as described here is not a physical network, but a
34 * programming concept used to implement all communication between
35 * components. Thus parts of this 'network' will model the on-chip
36 * connections between cache controllers and directory controllers as
37 * well as the links between chip and network switches.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__
41#define __MEM_RUBY_NETWORK_NETWORK_HH__
42
43#include <iostream>
44#include <string>
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The Network class is the base class for classes that implement the
31 * interconnection network between components (processor/cache
32 * components and memory/directory components). The interconnection
33 * network as described here is not a physical network, but a
34 * programming concept used to implement all communication between
35 * components. Thus parts of this 'network' will model the on-chip
36 * connections between cache controllers and directory controllers as
37 * well as the links between chip and network switches.
38 */
39
40#ifndef __MEM_RUBY_NETWORK_NETWORK_HH__
41#define __MEM_RUBY_NETWORK_NETWORK_HH__
42
43#include <iostream>
44#include <string>
|
| 45#include <vector>
|
45
46#include "mem/protocol/MessageSizeType.hh"
47#include "mem/ruby/common/Global.hh"
48#include "mem/ruby/system/NodeID.hh"
49#include "mem/ruby/system/System.hh"
50#include "params/RubyNetwork.hh"
51#include "sim/sim_object.hh"
52
53class NetDest;
54class MessageBuffer;
55class Throttle;
56class Topology;
57
58class Network : public SimObject
59{
60 public:
61 typedef RubyNetworkParams Params;
62 Network(const Params *p);
63 virtual ~Network() {}
64
65 virtual void init();
66
67 int getBufferSize() { return m_buffer_size; }
68 int getNumberOfVirtualNetworks() { return m_virtual_networks; }
69 int getEndpointBandwidth() { return m_endpoint_bandwidth; }
70 bool getAdaptiveRouting() {return m_adaptive_routing; }
71 int getLinkLatency() { return m_link_latency; }
72 int MessageSizeType_to_int(MessageSizeType size_type);
73
74 // returns the queue requested for the given component
75 virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered,
76 int netNumber) = 0;
77 virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered,
78 int netNumber) = 0;
| 46
47#include "mem/protocol/MessageSizeType.hh"
48#include "mem/ruby/common/Global.hh"
49#include "mem/ruby/system/NodeID.hh"
50#include "mem/ruby/system/System.hh"
51#include "params/RubyNetwork.hh"
52#include "sim/sim_object.hh"
53
54class NetDest;
55class MessageBuffer;
56class Throttle;
57class Topology;
58
59class Network : public SimObject
60{
61 public:
62 typedef RubyNetworkParams Params;
63 Network(const Params *p);
64 virtual ~Network() {}
65
66 virtual void init();
67
68 int getBufferSize() { return m_buffer_size; }
69 int getNumberOfVirtualNetworks() { return m_virtual_networks; }
70 int getEndpointBandwidth() { return m_endpoint_bandwidth; }
71 bool getAdaptiveRouting() {return m_adaptive_routing; }
72 int getLinkLatency() { return m_link_latency; }
73 int MessageSizeType_to_int(MessageSizeType size_type);
74
75 // returns the queue requested for the given component
76 virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered,
77 int netNumber) = 0;
78 virtual MessageBuffer* getFromNetQueue(NodeID id, bool ordered,
79 int netNumber) = 0;
|
79 virtual const Vector<Throttle*>* getThrottles(NodeID id) const;
| 80 virtual const std::vector<Throttle*>* getThrottles(NodeID id) const;
|
80 virtual int getNumNodes() {return 1;}
81
82 virtual void makeOutLink(SwitchID src, NodeID dest,
83 const NetDest& routing_table_entry, int link_latency, int link_weight,
84 int bw_multiplier, bool isReconfiguration) = 0;
85 virtual void makeInLink(SwitchID src, NodeID dest,
86 const NetDest& routing_table_entry, int link_latency,
87 int bw_multiplier, bool isReconfiguration) = 0;
88 virtual void makeInternalLink(SwitchID src, NodeID dest,
89 const NetDest& routing_table_entry, int link_latency, int link_weight,
90 int bw_multiplier, bool isReconfiguration) = 0;
91
92 virtual void reset() = 0;
93
94 virtual void printStats(std::ostream& out) const = 0;
95 virtual void clearStats() = 0;
96 virtual void printConfig(std::ostream& out) const = 0;
97 virtual void print(std::ostream& out) const = 0;
98
99 protected:
100 // Private copy constructor and assignment operator
101 Network(const Network& obj);
102 Network& operator=(const Network& obj);
103
104 protected:
105 const std::string m_name;
106 int m_nodes;
107 int m_virtual_networks;
108 int m_buffer_size;
109 int m_endpoint_bandwidth;
110 Topology* m_topology_ptr;
111 bool m_adaptive_routing;
112 int m_link_latency;
113 int m_control_msg_size;
114 int m_data_msg_size;
115};
116
117inline std::ostream&
118operator<<(std::ostream& out, const Network& obj)
119{
120 obj.print(out);
121 out << std::flush;
122 return out;
123}
124
125#endif // __MEM_RUBY_NETWORK_NETWORK_HH__
| 81 virtual int getNumNodes() {return 1;}
82
83 virtual void makeOutLink(SwitchID src, NodeID dest,
84 const NetDest& routing_table_entry, int link_latency, int link_weight,
85 int bw_multiplier, bool isReconfiguration) = 0;
86 virtual void makeInLink(SwitchID src, NodeID dest,
87 const NetDest& routing_table_entry, int link_latency,
88 int bw_multiplier, bool isReconfiguration) = 0;
89 virtual void makeInternalLink(SwitchID src, NodeID dest,
90 const NetDest& routing_table_entry, int link_latency, int link_weight,
91 int bw_multiplier, bool isReconfiguration) = 0;
92
93 virtual void reset() = 0;
94
95 virtual void printStats(std::ostream& out) const = 0;
96 virtual void clearStats() = 0;
97 virtual void printConfig(std::ostream& out) const = 0;
98 virtual void print(std::ostream& out) const = 0;
99
100 protected:
101 // Private copy constructor and assignment operator
102 Network(const Network& obj);
103 Network& operator=(const Network& obj);
104
105 protected:
106 const std::string m_name;
107 int m_nodes;
108 int m_virtual_networks;
109 int m_buffer_size;
110 int m_endpoint_bandwidth;
111 Topology* m_topology_ptr;
112 bool m_adaptive_routing;
113 int m_link_latency;
114 int m_control_msg_size;
115 int m_data_msg_size;
116};
117
118inline std::ostream&
119operator<<(std::ostream& out, const Network& obj)
120{
121 obj.print(out);
122 out << std::flush;
123 return out;
124}
125
126#endif // __MEM_RUBY_NETWORK_NETWORK_HH__
|