1/*
2 * Copyright (c) 2012,2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40#ifndef __MEM_QPORT_HH__
41#define __MEM_QPORT_HH__
42
43/**
44 * @file
45 * Declaration of the queued port.
46 */
47
48#include "mem/packet_queue.hh"
49#include "mem/port.hh"
| 1/*
2 * Copyright (c) 2012,2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40#ifndef __MEM_QPORT_HH__
41#define __MEM_QPORT_HH__
42
43/**
44 * @file
45 * Declaration of the queued port.
46 */
47
48#include "mem/packet_queue.hh"
49#include "mem/port.hh"
|
| 50#include "sim/sim_object.hh"
|
50
51/**
52 * A queued port is a port that has an infinite queue for outgoing
53 * packets and thus decouples the module that wants to send
54 * request/responses from the flow control (retry mechanism) of the
55 * port. A queued port can be used by both a master and a slave. The
56 * queue is a parameter to allow tailoring of the queue implementation
57 * (used in the cache).
58 */
59class QueuedSlavePort : public SlavePort
60{
61
62 protected:
63
64 /** Packet queue used to store outgoing responses. */
65 RespPacketQueue &respQueue;
66
67 void recvRespRetry() { respQueue.retry(); }
68
69 public:
70
71 /**
72 * Create a QueuedPort with a given name, owner, and a supplied
73 * implementation of a packet queue. The external definition of
74 * the queue enables e.g. the cache to implement a specific queue
75 * behaviuor in a subclass, and provide the latter to the
76 * QueuePort constructor.
77 */
| 51
52/**
53 * A queued port is a port that has an infinite queue for outgoing
54 * packets and thus decouples the module that wants to send
55 * request/responses from the flow control (retry mechanism) of the
56 * port. A queued port can be used by both a master and a slave. The
57 * queue is a parameter to allow tailoring of the queue implementation
58 * (used in the cache).
59 */
60class QueuedSlavePort : public SlavePort
61{
62
63 protected:
64
65 /** Packet queue used to store outgoing responses. */
66 RespPacketQueue &respQueue;
67
68 void recvRespRetry() { respQueue.retry(); }
69
70 public:
71
72 /**
73 * Create a QueuedPort with a given name, owner, and a supplied
74 * implementation of a packet queue. The external definition of
75 * the queue enables e.g. the cache to implement a specific queue
76 * behaviuor in a subclass, and provide the latter to the
77 * QueuePort constructor.
78 */
|
78 QueuedSlavePort(const std::string& name, MemObject* owner,
| 79 QueuedSlavePort(const std::string& name, SimObject* owner,
|
79 RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
80 SlavePort(name, owner, id), respQueue(resp_queue)
81 { }
82
83 virtual ~QueuedSlavePort() { }
84
85 /**
86 * Schedule the sending of a timing response.
87 *
88 * @param pkt Packet to send
89 * @param when Absolute time (in ticks) to send packet
90 */
91 void schedTimingResp(PacketPtr pkt, Tick when)
92 { respQueue.schedSendTiming(pkt, when); }
93
94 /** Check the list of buffered packets against the supplied
95 * functional request. */
96 bool trySatisfyFunctional(PacketPtr pkt)
97 { return respQueue.trySatisfyFunctional(pkt); }
98};
99
100/**
101 * The QueuedMasterPort combines two queues, a request queue and a
102 * snoop response queue, that both share the same port. The flow
103 * control for requests and snoop responses are completely
104 * independent, and so each queue manages its own flow control
105 * (retries).
106 */
107class QueuedMasterPort : public MasterPort
108{
109
110 protected:
111
112 /** Packet queue used to store outgoing requests. */
113 ReqPacketQueue &reqQueue;
114
115 /** Packet queue used to store outgoing snoop responses. */
116 SnoopRespPacketQueue &snoopRespQueue;
117
118 void recvReqRetry() { reqQueue.retry(); }
119
120 void recvRetrySnoopResp() { snoopRespQueue.retry(); }
121
122 public:
123
124 /**
125 * Create a QueuedPort with a given name, owner, and a supplied
126 * implementation of two packet queues. The external definition of
127 * the queues enables e.g. the cache to implement a specific queue
128 * behaviuor in a subclass, and provide the latter to the
129 * QueuePort constructor.
130 */
| 80 RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
81 SlavePort(name, owner, id), respQueue(resp_queue)
82 { }
83
84 virtual ~QueuedSlavePort() { }
85
86 /**
87 * Schedule the sending of a timing response.
88 *
89 * @param pkt Packet to send
90 * @param when Absolute time (in ticks) to send packet
91 */
92 void schedTimingResp(PacketPtr pkt, Tick when)
93 { respQueue.schedSendTiming(pkt, when); }
94
95 /** Check the list of buffered packets against the supplied
96 * functional request. */
97 bool trySatisfyFunctional(PacketPtr pkt)
98 { return respQueue.trySatisfyFunctional(pkt); }
99};
100
101/**
102 * The QueuedMasterPort combines two queues, a request queue and a
103 * snoop response queue, that both share the same port. The flow
104 * control for requests and snoop responses are completely
105 * independent, and so each queue manages its own flow control
106 * (retries).
107 */
108class QueuedMasterPort : public MasterPort
109{
110
111 protected:
112
113 /** Packet queue used to store outgoing requests. */
114 ReqPacketQueue &reqQueue;
115
116 /** Packet queue used to store outgoing snoop responses. */
117 SnoopRespPacketQueue &snoopRespQueue;
118
119 void recvReqRetry() { reqQueue.retry(); }
120
121 void recvRetrySnoopResp() { snoopRespQueue.retry(); }
122
123 public:
124
125 /**
126 * Create a QueuedPort with a given name, owner, and a supplied
127 * implementation of two packet queues. The external definition of
128 * the queues enables e.g. the cache to implement a specific queue
129 * behaviuor in a subclass, and provide the latter to the
130 * QueuePort constructor.
131 */
|
131 QueuedMasterPort(const std::string& name, MemObject* owner,
| 132 QueuedMasterPort(const std::string& name, SimObject* owner,
|
132 ReqPacketQueue &req_queue,
133 SnoopRespPacketQueue &snoop_resp_queue,
134 PortID id = InvalidPortID) :
135 MasterPort(name, owner, id), reqQueue(req_queue),
136 snoopRespQueue(snoop_resp_queue)
137 { }
138
139 virtual ~QueuedMasterPort() { }
140
141 /**
142 * Schedule the sending of a timing request.
143 *
144 * @param pkt Packet to send
145 * @param when Absolute time (in ticks) to send packet
146 */
147 void schedTimingReq(PacketPtr pkt, Tick when)
148 { reqQueue.schedSendTiming(pkt, when); }
149
150 /**
151 * Schedule the sending of a timing snoop response.
152 *
153 * @param pkt Packet to send
154 * @param when Absolute time (in ticks) to send packet
155 */
156 void schedTimingSnoopResp(PacketPtr pkt, Tick when)
157 { snoopRespQueue.schedSendTiming(pkt, when); }
158
159 /** Check the list of buffered packets against the supplied
160 * functional request. */
161 bool trySatisfyFunctional(PacketPtr pkt)
162 {
163 return reqQueue.trySatisfyFunctional(pkt) ||
164 snoopRespQueue.trySatisfyFunctional(pkt);
165 }
166};
167
168#endif // __MEM_QPORT_HH__
| 133 ReqPacketQueue &req_queue,
134 SnoopRespPacketQueue &snoop_resp_queue,
135 PortID id = InvalidPortID) :
136 MasterPort(name, owner, id), reqQueue(req_queue),
137 snoopRespQueue(snoop_resp_queue)
138 { }
139
140 virtual ~QueuedMasterPort() { }
141
142 /**
143 * Schedule the sending of a timing request.
144 *
145 * @param pkt Packet to send
146 * @param when Absolute time (in ticks) to send packet
147 */
148 void schedTimingReq(PacketPtr pkt, Tick when)
149 { reqQueue.schedSendTiming(pkt, when); }
150
151 /**
152 * Schedule the sending of a timing snoop response.
153 *
154 * @param pkt Packet to send
155 * @param when Absolute time (in ticks) to send packet
156 */
157 void schedTimingSnoopResp(PacketPtr pkt, Tick when)
158 { snoopRespQueue.schedSendTiming(pkt, when); }
159
160 /** Check the list of buffered packets against the supplied
161 * functional request. */
162 bool trySatisfyFunctional(PacketPtr pkt)
163 {
164 return reqQueue.trySatisfyFunctional(pkt) ||
165 snoopRespQueue.trySatisfyFunctional(pkt);
166 }
167};
168
169#endif // __MEM_QPORT_HH__
|