port_proxy.hh (12532:a86ce386add1) | port_proxy.hh (13893:0e863b6c441a) |
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1/* 2 * Copyright (c) 2011-2013, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 45 unchanged lines hidden (view full) --- 54 * CPU, e.g. for threads) and thus are transparent to a potentially 55 * distributed memory and automatically adhere to the memory map of 56 * the system. 57 */ 58 59#ifndef __MEM_PORT_PROXY_HH__ 60#define __MEM_PORT_PROXY_HH__ 61 | 1/* 2 * Copyright (c) 2011-2013, 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 45 unchanged lines hidden (view full) --- 54 * CPU, e.g. for threads) and thus are transparent to a potentially 55 * distributed memory and automatically adhere to the memory map of 56 * the system. 57 */ 58 59#ifndef __MEM_PORT_PROXY_HH__ 60#define __MEM_PORT_PROXY_HH__ 61 |
62#include "config/the_isa.hh" 63#if THE_ISA != NULL_ISA 64 #include "arch/isa_traits.hh" 65#endif 66 | |
67#include "mem/port.hh" 68#include "sim/byteswap.hh" 69 70/** 71 * This object is a proxy for a structural port, to be used for debug 72 * accesses. 73 * 74 * This proxy object is used when non structural entities --- 13 unchanged lines hidden (view full) --- 88 /** The actual physical port used by this proxy. */ 89 MasterPort &_port; 90 91 /** Granularity of any transactions issued through this proxy. */ 92 const unsigned int _cacheLineSize; 93 94 public: 95 PortProxy(MasterPort &port, unsigned int cacheLineSize) : | 62#include "mem/port.hh" 63#include "sim/byteswap.hh" 64 65/** 66 * This object is a proxy for a structural port, to be used for debug 67 * accesses. 68 * 69 * This proxy object is used when non structural entities --- 13 unchanged lines hidden (view full) --- 83 /** The actual physical port used by this proxy. */ 84 MasterPort &_port; 85 86 /** Granularity of any transactions issued through this proxy. */ 87 const unsigned int _cacheLineSize; 88 89 public: 90 PortProxy(MasterPort &port, unsigned int cacheLineSize) : |
96 _port(port), _cacheLineSize(cacheLineSize) { } | 91 _port(port), _cacheLineSize(cacheLineSize) 92 {} |
97 virtual ~PortProxy() { } 98 99 /** 100 * Read size bytes memory at address and store in p. 101 */ | 93 virtual ~PortProxy() { } 94 95 /** 96 * Read size bytes memory at address and store in p. 97 */ |
102 virtual void readBlob(Addr addr, uint8_t* p, int size) const { | 98 virtual void 99 readBlob(Addr addr, uint8_t* p, int size) const 100 { |
103 readBlobPhys(addr, 0, p, size); 104 } 105 106 /** 107 * Write size bytes from p to address. 108 */ | 101 readBlobPhys(addr, 0, p, size); 102 } 103 104 /** 105 * Write size bytes from p to address. 106 */ |
109 virtual void writeBlob(Addr addr, const uint8_t* p, int size) const { | 107 virtual void 108 writeBlob(Addr addr, const uint8_t* p, int size) const 109 { |
110 writeBlobPhys(addr, 0, p, size); 111 } 112 113 /** 114 * Fill size bytes starting at addr with byte value val. 115 */ | 110 writeBlobPhys(addr, 0, p, size); 111 } 112 113 /** 114 * Fill size bytes starting at addr with byte value val. 115 */ |
116 virtual void memsetBlob(Addr addr, uint8_t v, int size) const { | 116 virtual void 117 memsetBlob(Addr addr, uint8_t v, int size) const 118 { |
117 memsetBlobPhys(addr, 0, v, size); 118 } 119 120 /** 121 * Read size bytes memory at physical address and store in p. 122 */ 123 void readBlobPhys(Addr addr, Request::Flags flags, 124 uint8_t* p, int size) const; --- 19 unchanged lines hidden (view full) --- 144 /** 145 * Write object T to address. Writes sizeof(T) bytes. 146 */ 147 template <typename T> 148 void write(Addr address, T data) const; 149 150 /** 151 * Read sizeof(T) bytes from address and return as object T. | 119 memsetBlobPhys(addr, 0, v, size); 120 } 121 122 /** 123 * Read size bytes memory at physical address and store in p. 124 */ 125 void readBlobPhys(Addr addr, Request::Flags flags, 126 uint8_t* p, int size) const; --- 19 unchanged lines hidden (view full) --- 146 /** 147 * Write object T to address. Writes sizeof(T) bytes. 148 */ 149 template <typename T> 150 void write(Addr address, T data) const; 151 152 /** 153 * Read sizeof(T) bytes from address and return as object T. |
152 * Performs selected endianness transform. | 154 * Performs endianness conversion from the selected guest to host order. |
153 */ 154 template <typename T> | 155 */ 156 template <typename T> |
155 T readGtoH(Addr address, ByteOrder guest_byte_order) const; | 157 T read(Addr address, ByteOrder guest_byte_order) const; |
156 157 /** 158 * Write object T to address. Writes sizeof(T) bytes. | 158 159 /** 160 * Write object T to address. Writes sizeof(T) bytes. |
159 * Performs selected endianness transform. | 161 * Performs endianness conversion from host to the selected guest order. |
160 */ 161 template <typename T> | 162 */ 163 template <typename T> |
162 void writeHtoG(Addr address, T data, ByteOrder guest_byte_order) const; 163 164#if THE_ISA != NULL_ISA 165 /** 166 * Read sizeof(T) bytes from address and return as object T. 167 * Performs Guest to Host endianness transform. 168 */ 169 template <typename T> 170 T readGtoH(Addr address) const; 171 172 /** 173 * Write object T to address. Writes sizeof(T) bytes. 174 * Performs Host to Guest endianness transform. 175 */ 176 template <typename T> 177 void writeHtoG(Addr address, T data) const; 178#endif | 164 void write(Addr address, T data, ByteOrder guest_byte_order) const; |
179}; 180 181 182/** 183 * This object is a proxy for a structural port, to be used for debug 184 * accesses to secure memory. 185 * 186 * The addresses are interpreted as physical addresses to secure memory. --- 22 unchanged lines hidden (view full) --- 209void 210PortProxy::write(Addr address, T data) const 211{ 212 writeBlob(address, (uint8_t*)&data, sizeof(T)); 213} 214 215template <typename T> 216T | 165}; 166 167 168/** 169 * This object is a proxy for a structural port, to be used for debug 170 * accesses to secure memory. 171 * 172 * The addresses are interpreted as physical addresses to secure memory. --- 22 unchanged lines hidden (view full) --- 195void 196PortProxy::write(Addr address, T data) const 197{ 198 writeBlob(address, (uint8_t*)&data, sizeof(T)); 199} 200 201template <typename T> 202T |
217PortProxy::readGtoH(Addr address, ByteOrder byte_order) const | 203PortProxy::read(Addr address, ByteOrder byte_order) const |
218{ 219 T data; 220 readBlob(address, (uint8_t*)&data, sizeof(T)); 221 return gtoh(data, byte_order); 222} 223 224template <typename T> 225void | 204{ 205 T data; 206 readBlob(address, (uint8_t*)&data, sizeof(T)); 207 return gtoh(data, byte_order); 208} 209 210template <typename T> 211void |
226PortProxy::writeHtoG(Addr address, T data, ByteOrder byte_order) const | 212PortProxy::write(Addr address, T data, ByteOrder byte_order) const |
227{ 228 data = htog(data, byte_order); 229 writeBlob(address, (uint8_t*)&data, sizeof(T)); 230} 231 | 213{ 214 data = htog(data, byte_order); 215 writeBlob(address, (uint8_t*)&data, sizeof(T)); 216} 217 |
232#if THE_ISA != NULL_ISA 233template <typename T> 234T 235PortProxy::readGtoH(Addr address) const 236{ 237 T data; 238 readBlob(address, (uint8_t*)&data, sizeof(T)); 239 return TheISA::gtoh(data); 240} 241 242template <typename T> 243void 244PortProxy::writeHtoG(Addr address, T data) const 245{ 246 data = TheISA::htog(data); 247 writeBlob(address, (uint8_t*)&data, sizeof(T)); 248} 249#endif 250 | |
251#endif // __MEM_PORT_PROXY_HH__ | 218#endif // __MEM_PORT_PROXY_HH__ |