port_proxy.hh (13893:0e863b6c441a) port_proxy.hh (14007:36f842f523c6)
1/*
2 * Copyright (c) 2011-2013, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40/**
41 * @file
42 * PortProxy Object Declaration.
43 *
44 * Port proxies are used when non-structural entities need access to
45 * the memory system (or structural entities that want to peak into
46 * the memory system without making a real memory access).
47 *
48 * Proxy objects replace the previous FunctionalPort, TranslatingPort
49 * and VirtualPort objects, which provided the same functionality as
50 * the proxies, but were instances of ports not corresponding to real
51 * structural ports of the simulated system. Via the port proxies all
52 * the accesses go through an actual port (either the system port,
53 * e.g. for processes or initialisation, or a the data port of the
54 * CPU, e.g. for threads) and thus are transparent to a potentially
55 * distributed memory and automatically adhere to the memory map of
56 * the system.
57 */
58
59#ifndef __MEM_PORT_PROXY_HH__
60#define __MEM_PORT_PROXY_HH__
61
62#include "mem/port.hh"
63#include "sim/byteswap.hh"
64
65/**
66 * This object is a proxy for a structural port, to be used for debug
67 * accesses.
68 *
69 * This proxy object is used when non structural entities
70 * (e.g. thread contexts, object file loaders) need access to the
71 * memory system. It calls the corresponding functions on the underlying
72 * structural port, and provides templatized convenience access functions.
73 *
74 * The addresses are interpreted as physical addresses.
75 *
76 * @sa SETranslatingProxy
77 * @sa FSTranslatingProxy
78 */
79class PortProxy
80{
81 private:
82
83 /** The actual physical port used by this proxy. */
84 MasterPort &_port;
85
86 /** Granularity of any transactions issued through this proxy. */
87 const unsigned int _cacheLineSize;
88
89 public:
90 PortProxy(MasterPort &port, unsigned int cacheLineSize) :
91 _port(port), _cacheLineSize(cacheLineSize)
92 {}
93 virtual ~PortProxy() { }
94
95 /**
96 * Read size bytes memory at address and store in p.
97 */
98 virtual void
99 readBlob(Addr addr, uint8_t* p, int size) const
100 {
101 readBlobPhys(addr, 0, p, size);
102 }
103
104 /**
105 * Write size bytes from p to address.
106 */
107 virtual void
108 writeBlob(Addr addr, const uint8_t* p, int size) const
109 {
110 writeBlobPhys(addr, 0, p, size);
111 }
112
113 /**
114 * Fill size bytes starting at addr with byte value val.
115 */
116 virtual void
117 memsetBlob(Addr addr, uint8_t v, int size) const
118 {
119 memsetBlobPhys(addr, 0, v, size);
120 }
121
122 /**
123 * Read size bytes memory at physical address and store in p.
124 */
125 void readBlobPhys(Addr addr, Request::Flags flags,
126 uint8_t* p, int size) const;
127
128 /**
129 * Write size bytes from p to physical address.
130 */
131 void writeBlobPhys(Addr addr, Request::Flags flags,
132 const uint8_t* p, int size) const;
133
134 /**
135 * Fill size bytes starting at physical addr with byte value val.
136 */
137 void memsetBlobPhys(Addr addr, Request::Flags flags,
138 uint8_t v, int size) const;
139
140 /**
141 * Read sizeof(T) bytes from address and return as object T.
142 */
143 template <typename T>
144 T read(Addr address) const;
145
146 /**
147 * Write object T to address. Writes sizeof(T) bytes.
148 */
149 template <typename T>
150 void write(Addr address, T data) const;
151
152 /**
153 * Read sizeof(T) bytes from address and return as object T.
154 * Performs endianness conversion from the selected guest to host order.
155 */
156 template <typename T>
157 T read(Addr address, ByteOrder guest_byte_order) const;
158
159 /**
160 * Write object T to address. Writes sizeof(T) bytes.
161 * Performs endianness conversion from host to the selected guest order.
162 */
163 template <typename T>
164 void write(Addr address, T data, ByteOrder guest_byte_order) const;
165};
166
167
1/*
2 * Copyright (c) 2011-2013, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40/**
41 * @file
42 * PortProxy Object Declaration.
43 *
44 * Port proxies are used when non-structural entities need access to
45 * the memory system (or structural entities that want to peak into
46 * the memory system without making a real memory access).
47 *
48 * Proxy objects replace the previous FunctionalPort, TranslatingPort
49 * and VirtualPort objects, which provided the same functionality as
50 * the proxies, but were instances of ports not corresponding to real
51 * structural ports of the simulated system. Via the port proxies all
52 * the accesses go through an actual port (either the system port,
53 * e.g. for processes or initialisation, or a the data port of the
54 * CPU, e.g. for threads) and thus are transparent to a potentially
55 * distributed memory and automatically adhere to the memory map of
56 * the system.
57 */
58
59#ifndef __MEM_PORT_PROXY_HH__
60#define __MEM_PORT_PROXY_HH__
61
62#include "mem/port.hh"
63#include "sim/byteswap.hh"
64
65/**
66 * This object is a proxy for a structural port, to be used for debug
67 * accesses.
68 *
69 * This proxy object is used when non structural entities
70 * (e.g. thread contexts, object file loaders) need access to the
71 * memory system. It calls the corresponding functions on the underlying
72 * structural port, and provides templatized convenience access functions.
73 *
74 * The addresses are interpreted as physical addresses.
75 *
76 * @sa SETranslatingProxy
77 * @sa FSTranslatingProxy
78 */
79class PortProxy
80{
81 private:
82
83 /** The actual physical port used by this proxy. */
84 MasterPort &_port;
85
86 /** Granularity of any transactions issued through this proxy. */
87 const unsigned int _cacheLineSize;
88
89 public:
90 PortProxy(MasterPort &port, unsigned int cacheLineSize) :
91 _port(port), _cacheLineSize(cacheLineSize)
92 {}
93 virtual ~PortProxy() { }
94
95 /**
96 * Read size bytes memory at address and store in p.
97 */
98 virtual void
99 readBlob(Addr addr, uint8_t* p, int size) const
100 {
101 readBlobPhys(addr, 0, p, size);
102 }
103
104 /**
105 * Write size bytes from p to address.
106 */
107 virtual void
108 writeBlob(Addr addr, const uint8_t* p, int size) const
109 {
110 writeBlobPhys(addr, 0, p, size);
111 }
112
113 /**
114 * Fill size bytes starting at addr with byte value val.
115 */
116 virtual void
117 memsetBlob(Addr addr, uint8_t v, int size) const
118 {
119 memsetBlobPhys(addr, 0, v, size);
120 }
121
122 /**
123 * Read size bytes memory at physical address and store in p.
124 */
125 void readBlobPhys(Addr addr, Request::Flags flags,
126 uint8_t* p, int size) const;
127
128 /**
129 * Write size bytes from p to physical address.
130 */
131 void writeBlobPhys(Addr addr, Request::Flags flags,
132 const uint8_t* p, int size) const;
133
134 /**
135 * Fill size bytes starting at physical addr with byte value val.
136 */
137 void memsetBlobPhys(Addr addr, Request::Flags flags,
138 uint8_t v, int size) const;
139
140 /**
141 * Read sizeof(T) bytes from address and return as object T.
142 */
143 template <typename T>
144 T read(Addr address) const;
145
146 /**
147 * Write object T to address. Writes sizeof(T) bytes.
148 */
149 template <typename T>
150 void write(Addr address, T data) const;
151
152 /**
153 * Read sizeof(T) bytes from address and return as object T.
154 * Performs endianness conversion from the selected guest to host order.
155 */
156 template <typename T>
157 T read(Addr address, ByteOrder guest_byte_order) const;
158
159 /**
160 * Write object T to address. Writes sizeof(T) bytes.
161 * Performs endianness conversion from host to the selected guest order.
162 */
163 template <typename T>
164 void write(Addr address, T data, ByteOrder guest_byte_order) const;
165};
166
167
168/**
169 * This object is a proxy for a structural port, to be used for debug
170 * accesses to secure memory.
171 *
172 * The addresses are interpreted as physical addresses to secure memory.
173 */
174class SecurePortProxy : public PortProxy
175{
176 public:
177 SecurePortProxy(MasterPort &port, unsigned int cache_line_size)
178 : PortProxy(port, cache_line_size) {}
179
180 void readBlob(Addr addr, uint8_t *p, int size) const override;
181 void writeBlob(Addr addr, const uint8_t *p, int size) const override;
182 void memsetBlob(Addr addr, uint8_t val, int size) const override;
183};
184
185template <typename T>
186T
187PortProxy::read(Addr address) const
188{
189 T data;
190 readBlob(address, (uint8_t*)&data, sizeof(T));
191 return data;
192}
193
194template <typename T>
195void
196PortProxy::write(Addr address, T data) const
197{
198 writeBlob(address, (uint8_t*)&data, sizeof(T));
199}
200
201template <typename T>
202T
203PortProxy::read(Addr address, ByteOrder byte_order) const
204{
205 T data;
206 readBlob(address, (uint8_t*)&data, sizeof(T));
207 return gtoh(data, byte_order);
208}
209
210template <typename T>
211void
212PortProxy::write(Addr address, T data, ByteOrder byte_order) const
213{
214 data = htog(data, byte_order);
215 writeBlob(address, (uint8_t*)&data, sizeof(T));
216}
217
218#endif // __MEM_PORT_PROXY_HH__
168template <typename T>
169T
170PortProxy::read(Addr address) const
171{
172 T data;
173 readBlob(address, (uint8_t*)&data, sizeof(T));
174 return data;
175}
176
177template <typename T>
178void
179PortProxy::write(Addr address, T data) const
180{
181 writeBlob(address, (uint8_t*)&data, sizeof(T));
182}
183
184template <typename T>
185T
186PortProxy::read(Addr address, ByteOrder byte_order) const
187{
188 T data;
189 readBlob(address, (uint8_t*)&data, sizeof(T));
190 return gtoh(data, byte_order);
191}
192
193template <typename T>
194void
195PortProxy::write(Addr address, T data, ByteOrder byte_order) const
196{
197 data = htog(data, byte_order);
198 writeBlob(address, (uint8_t*)&data, sizeof(T));
199}
200
201#endif // __MEM_PORT_PROXY_HH__