1/*
2 * Copyright (c) 2011-2013, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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54 * CPU, e.g. for threads) and thus are transparent to a potentially
55 * distributed memory and automatically adhere to the memory map of
56 * the system.
57 */
58
59#ifndef __MEM_PORT_PROXY_HH__
60#define __MEM_PORT_PROXY_HH__
61
62#include <limits>
63
64#include "mem/port.hh"
65#include "sim/byteswap.hh"
66
67/**
68 * This object is a proxy for a structural port, to be used for debug
69 * accesses.
70 *
71 * This proxy object is used when non structural entities
72 * (e.g. thread contexts, object file loaders) need access to the
73 * memory system. It calls the corresponding functions on the underlying
74 * structural port, and provides templatized convenience access functions.
75 *
76 * The addresses are interpreted as physical addresses.
77 *
78 * @sa SETranslatingProxy
79 * @sa FSTranslatingProxy
80 */
81class PortProxy
82{
83 private:
84
85 /** The actual physical port used by this proxy. */
86 MasterPort &_port;
87
88 /** Granularity of any transactions issued through this proxy. */
89 const unsigned int _cacheLineSize;
90
91 public:
92 PortProxy(MasterPort &port, unsigned int cacheLineSize) :
93 _port(port), _cacheLineSize(cacheLineSize)
94 {}
95 virtual ~PortProxy() { }
96
97
98
99 /** Fixed functionality for use in base classes. */
100
101 /**
102 * Read size bytes memory at physical address and store in p.

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