port.hh (2632:1bb2f91485ea) port.hh (2640:266b80dd5eca)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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64 * have to be created.
65 *
66 * Recv accesor functions are being called from the peer interface.
67 * Send accessor functions are being called from the device the port is
68 * associated with, and it will call the peer recv. accessor function.
69 */
70class Port
71{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 55 unchanged lines hidden (view full) ---

64 * have to be created.
65 *
66 * Recv accesor functions are being called from the peer interface.
67 * Send accessor functions are being called from the device the port is
68 * associated with, and it will call the peer recv. accessor function.
69 */
70class Port
71{
72 private:
73
74 /** Descriptive name (for DPRINTF output) */
75 const std::string portName;
76
72 public:
73
77 public:
78
79 /**
80 * Constructor.
81 *
82 * @param _name Port name for DPRINTF output. Should include name
83 * of memory system object to which the port belongs.
84 */
85 Port(const std::string &_name)
86 : portName(_name)
87 { }
88
89 /** Return port name (for DPRINTF). */
90 const std::string &name() const { return portName; }
91
74 virtual ~Port() {};
92 virtual ~Port() {};
93
75 // mey be better to use subclasses & RTTI?
76 /** Holds the ports status. Keeps track if it is blocked, or has
77 calculated a range change. */
78 enum Status {
79 Blocked,
80 Unblocked,
81 RangeChange
82 };

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219/** A simple functional port that is only meant for one way communication to
220 * physical memory. It is only meant to be used to load data into memory before
221 * the simulation begins.
222 */
223
224class FunctionalPort : public Port
225{
226 public:
94 // mey be better to use subclasses & RTTI?
95 /** Holds the ports status. Keeps track if it is blocked, or has
96 calculated a range change. */
97 enum Status {
98 Blocked,
99 Unblocked,
100 RangeChange
101 };

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238/** A simple functional port that is only meant for one way communication to
239 * physical memory. It is only meant to be used to load data into memory before
240 * the simulation begins.
241 */
242
243class FunctionalPort : public Port
244{
245 public:
246 FunctionalPort(const std::string &_name)
247 : Port(_name)
248 {}
249
227 virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); }
228 virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); }
229 virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); }
230 virtual void recvStatusChange(Status status) {}
231
232 template <typename T>
233 inline void write(Addr addr, T d)
234 {

--- 13 unchanged lines hidden --- 		250 virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); }
251 virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); }
252 virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); }
253 virtual void recvStatusChange(Status status) {}
254
255 template <typename T>
256 inline void write(Addr addr, T d)
257 {

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