port.hh (13845:60939226a345) port.hh (13892:0182a0601f66)
1/*
2 * Copyright (c) 2011-2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50#ifndef __MEM_PORT_HH__
51#define __MEM_PORT_HH__
52
53#include "base/addr_range.hh"
54#include "mem/backdoor.hh"
55#include "mem/packet.hh"
56#include "sim/port.hh"
57
1/*
2 * Copyright (c) 2011-2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50#ifndef __MEM_PORT_HH__
51#define __MEM_PORT_HH__
52
53#include "base/addr_range.hh"
54#include "mem/backdoor.hh"
55#include "mem/packet.hh"
56#include "sim/port.hh"
57
58class MemObject;
58class SimObject;
59
60/** Forward declaration */
61class BaseSlavePort;
62
63/**
64 * A BaseMasterPort is a protocol-agnostic master port, responsible
65 * only for the structural connection to a slave port. The final
66 * master port that inherits from the base class must override the

--- 51 unchanged lines hidden (view full) ---

118 friend class SlavePort;
119
120 private:
121
122 SlavePort* _slavePort;
123
124 protected:
125
59
60/** Forward declaration */
61class BaseSlavePort;
62
63/**
64 * A BaseMasterPort is a protocol-agnostic master port, responsible
65 * only for the structural connection to a slave port. The final
66 * master port that inherits from the base class must override the

--- 51 unchanged lines hidden (view full) ---

118 friend class SlavePort;
119
120 private:
121
122 SlavePort* _slavePort;
123
124 protected:
125
126 MemObject& owner;
126 SimObject& owner;
127
128 public:
129
127
128 public:
129
130 MasterPort(const std::string& name, MemObject* _owner,
130 MasterPort(const std::string& name, SimObject* _owner,
131 PortID id=InvalidPortID);
132 virtual ~MasterPort();
133
134 /**
135 * Bind this master port to a slave port. This also does the
136 * mirror action and binds the slave port to the master port.
137 */
138 void bind(Port &peer) override;

--- 173 unchanged lines hidden (view full) ---

312
313 private:
314
315 MasterPort* _masterPort;
316 bool defaultBackdoorWarned;
317
318 protected:
319
131 PortID id=InvalidPortID);
132 virtual ~MasterPort();
133
134 /**
135 * Bind this master port to a slave port. This also does the
136 * mirror action and binds the slave port to the master port.
137 */
138 void bind(Port &peer) override;

--- 173 unchanged lines hidden (view full) ---

312
313 private:
314
315 MasterPort* _masterPort;
316 bool defaultBackdoorWarned;
317
318 protected:
319
320 MemObject& owner;
320 SimObject& owner;
321
322 public:
323
321
322 public:
323
324 SlavePort(const std::string& name, MemObject* _owner,
324 SlavePort(const std::string& name, SimObject* _owner,
325 PortID id=InvalidPortID);
326 virtual ~SlavePort();
327
328 /**
329 * Send an atomic snoop request packet, where the data is moved
330 * and the state is updated in zero time, without interleaving
331 * with other memory accesses.
332 *

--- 140 unchanged lines hidden --- 		325 PortID id=InvalidPortID);
326 virtual ~SlavePort();
327
328 /**
329 * Send an atomic snoop request packet, where the data is moved
330 * and the state is updated in zero time, without interleaving
331 * with other memory accesses.
332 *

--- 140 unchanged lines hidden ---