port.hh (13771:10d990934f15) | port.hh (13782:9f6654f478e2) |
---|---|
1/* 2 * Copyright (c) 2011-2012,2015,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72 73 BaseSlavePort* _baseSlavePort; 74 75 BaseMasterPort(const std::string& name, PortID id=InvalidPortID); 76 virtual ~BaseMasterPort(); 77 78 public: 79 | 1/* 2 * Copyright (c) 2011-2012,2015,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72 73 BaseSlavePort* _baseSlavePort; 74 75 BaseMasterPort(const std::string& name, PortID id=InvalidPortID); 76 virtual ~BaseMasterPort(); 77 78 public: 79 |
80 virtual void bind(BaseSlavePort& slave_port) = 0; 81 virtual void unbind() = 0; | |
82 BaseSlavePort& getSlavePort() const; | 80 BaseSlavePort& getSlavePort() const; |
83 bool isConnected() const; | |
84 85}; 86 87/** 88 * A BaseSlavePort is a protocol-agnostic slave port, responsible 89 * only for the structural connection to a master port. 90 */ 91class BaseSlavePort : public Port --- 4 unchanged lines hidden (view full) --- 96 BaseMasterPort* _baseMasterPort; 97 98 BaseSlavePort(const std::string& name, PortID id=InvalidPortID); 99 virtual ~BaseSlavePort(); 100 101 public: 102 103 BaseMasterPort& getMasterPort() const; | 81 82}; 83 84/** 85 * A BaseSlavePort is a protocol-agnostic slave port, responsible 86 * only for the structural connection to a master port. 87 */ 88class BaseSlavePort : public Port --- 4 unchanged lines hidden (view full) --- 93 BaseMasterPort* _baseMasterPort; 94 95 BaseSlavePort(const std::string& name, PortID id=InvalidPortID); 96 virtual ~BaseSlavePort(); 97 98 public: 99 100 BaseMasterPort& getMasterPort() const; |
104 bool isConnected() const; | |
105 106}; 107 108/** Forward declaration */ 109class SlavePort; 110 111/** 112 * A MasterPort is a specialisation of a BaseMasterPort, which --- 20 unchanged lines hidden (view full) --- 133 MasterPort(const std::string& name, MemObject* _owner, 134 PortID id=InvalidPortID); 135 virtual ~MasterPort(); 136 137 /** 138 * Bind this master port to a slave port. This also does the 139 * mirror action and binds the slave port to the master port. 140 */ | 101 102}; 103 104/** Forward declaration */ 105class SlavePort; 106 107/** 108 * A MasterPort is a specialisation of a BaseMasterPort, which --- 20 unchanged lines hidden (view full) --- 129 MasterPort(const std::string& name, MemObject* _owner, 130 PortID id=InvalidPortID); 131 virtual ~MasterPort(); 132 133 /** 134 * Bind this master port to a slave port. This also does the 135 * mirror action and binds the slave port to the master port. 136 */ |
141 void bind(BaseSlavePort& slave_port); | 137 void bind(Port &peer) override; |
142 143 /** 144 * Unbind this master port and the associated slave port. 145 */ | 138 139 /** 140 * Unbind this master port and the associated slave port. 141 */ |
146 void unbind(); | 142 void unbind() override; |
147 148 /** 149 * Send an atomic request packet, where the data is moved and the 150 * state is updated in zero time, without interleaving with other 151 * memory accesses. 152 * 153 * @param pkt Packet to send. 154 * --- 234 unchanged lines hidden (view full) --- 389 * Get a list of the non-overlapping address ranges the owner is 390 * responsible for. All slave ports must override this function 391 * and return a populated list with at least one item. 392 * 393 * @return a list of ranges responded to 394 */ 395 virtual AddrRangeList getAddrRanges() const = 0; 396 | 143 144 /** 145 * Send an atomic request packet, where the data is moved and the 146 * state is updated in zero time, without interleaving with other 147 * memory accesses. 148 * 149 * @param pkt Packet to send. 150 * --- 234 unchanged lines hidden (view full) --- 385 * Get a list of the non-overlapping address ranges the owner is 386 * responsible for. All slave ports must override this function 387 * and return a populated list with at least one item. 388 * 389 * @return a list of ranges responded to 390 */ 391 virtual AddrRangeList getAddrRanges() const = 0; 392 |
393 /** 394 * We let the master port do the work, so these don't do anything. 395 */ 396 void unbind() override {} 397 void bind(Port &peer) override {} 398 |
|
397 protected: 398 399 /** 400 * Called by the master port to unbind. Should never be called 401 * directly. 402 */ | 399 protected: 400 401 /** 402 * Called by the master port to unbind. Should never be called 403 * directly. 404 */ |
403 void unbind(); | 405 void slaveUnbind(); |
404 405 /** 406 * Called by the master port to bind. Should never be called 407 * directly. 408 */ | 406 407 /** 408 * Called by the master port to bind. Should never be called 409 * directly. 410 */ |
409 void bind(MasterPort& master_port); | 411 void slaveBind(MasterPort& master_port); |
410 411 /** 412 * Receive an atomic request packet from the master port. 413 */ 414 virtual Tick recvAtomic(PacketPtr pkt) = 0; 415 416 /** 417 * Receive a functional request packet from the master port. --- 33 unchanged lines hidden --- | 412 413 /** 414 * Receive an atomic request packet from the master port. 415 */ 416 virtual Tick recvAtomic(PacketPtr pkt) = 0; 417 418 /** 419 * Receive a functional request packet from the master port. --- 33 unchanged lines hidden --- |