1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 235 unchanged lines hidden (view full) --- 244 : Port(_name) 245 {} 246 247 virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); } 248 virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); } 249 virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); } 250 virtual void recvStatusChange(Status status) {} 251 |
252 /** a write function that also does an endian conversion. */ |
253 template <typename T> |
254 inline void writeHtoG(Addr addr, T d); 255 256 /** a read function that also does an endian conversion. */ 257 template <typename T> 258 inline T readGtoH(Addr addr); 259 260 template <typename T> |
261 inline void write(Addr addr, T d) 262 { 263 writeBlob(addr, (uint8_t*)&d, sizeof(T)); 264 } 265 266 template <typename T> 267 inline T read(Addr addr) 268 { 269 T d; 270 readBlob(addr, (uint8_t*)&d, sizeof(T)); 271 return d; 272 } 273}; 274 275#endif //__MEM_PORT_HH__ |