1/* 2 * Copyright (c) 2011-2012,2015,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 protected: 74 BaseSlavePort *_baseSlavePort; 75 76 BaseMasterPort(const std::string &name, PortID id=InvalidPortID); 77 virtual ~BaseMasterPort(); 78 79 public: 80 BaseSlavePort& getSlavePort() const; |
81 void bind(Port &peer) override; 82 void unbind() override; |
83}; 84 85/** 86 * A BaseSlavePort is a protocol-agnostic slave port, responsible 87 * only for the structural connection to a master port. 88 */ 89class BaseSlavePort : public Port 90{ 91 protected: 92 BaseMasterPort *_baseMasterPort; 93 94 BaseSlavePort(const std::string &name, PortID id=InvalidPortID); 95 virtual ~BaseSlavePort(); 96 97 public: 98 BaseMasterPort& getMasterPort() const; |
99 void bind(Port &peer) override; 100 void unbind() override; |
101}; 102 103/** Forward declaration */ 104class SlavePort; 105 106/** 107 * A MasterPort is a specialisation of a BaseMasterPort, which 108 * implements the default protocol for the three different level of --- 401 unchanged lines hidden --- |