1/*
2 * Copyright (c) 2011-2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 protected:
74 BaseSlavePort *_baseSlavePort;
75
76 BaseMasterPort(const std::string &name, PortID id=InvalidPortID);
77 virtual ~BaseMasterPort();
78
79 public:
80 BaseSlavePort& getSlavePort() const;
81};
82
83/**
84 * A BaseSlavePort is a protocol-agnostic slave port, responsible
85 * only for the structural connection to a master port.
86 */
87class BaseSlavePort : public Port
88{
89 protected:
90 BaseMasterPort *_baseMasterPort;
91
92 BaseSlavePort(const std::string &name, PortID id=InvalidPortID);
93 virtual ~BaseSlavePort();
94
95 public:
96 BaseMasterPort& getMasterPort() const;
97};
98
99/** Forward declaration */
100class SlavePort;
101
102/**
103 * A MasterPort is a specialisation of a BaseMasterPort, which
104 * implements the default protocol for the three different level of

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