1/* 2 * Copyright (c) 2012,2015,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 35 unchanged lines hidden (view full) --- 44 45/** 46 * @file 47 * Port object definitions. 48 */ 49#include "mem/port.hh" 50 51#include "base/trace.hh" |
52#include "sim/sim_object.hh" |
53 54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id) 55 : Port(name, _id), _baseSlavePort(NULL) 56{ 57} 58 59BaseMasterPort::~BaseMasterPort() 60{ --- 26 unchanged lines hidden (view full) --- 87 name()); 88 89 return *_baseMasterPort; 90} 91 92/** 93 * Master port 94 */ |
95MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id) |
96 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner) 97{ 98} 99 100MasterPort::~MasterPort() 101{ 102} 103 --- 92 unchanged lines hidden (view full) --- 196 pkt.senderState = &prs; 197 198 sendFunctional(&pkt); 199} 200 201/** 202 * Slave port 203 */ |
204SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id) |
205 : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false), 206 owner(*_owner) 207{ 208} 209 210SlavePort::~SlavePort() 211{ 212} --- 66 unchanged lines hidden --- |