1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "base/trace.hh"
50#include "mem/mem_object.hh"
51#include "mem/port.hh"
52
53Port::Port(const std::string &_name, MemObject& _owner, PortID _id)
54 : portName(_name), id(_id), owner(_owner)
55{
56}
57
58Port::~Port()
59{
60}
61
62/**
63 * Master port
64 */
65MasterPort::MasterPort(const std::string& name, MemObject* owner, PortID _id)
66 : Port(name, *owner, _id), _slavePort(NULL)
67{
68}
69
70MasterPort::~MasterPort()
71{
72}
73
74SlavePort&
75MasterPort::getSlavePort() const
76{
77 if(_slavePort == NULL)
78 panic("Cannot getSlavePort on master port %s that is not connected\n",
79 name());
80
81 return *_slavePort;
82}
83
84void
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "base/trace.hh"
50#include "mem/mem_object.hh"
51#include "mem/port.hh"
52
53Port::Port(const std::string &_name, MemObject& _owner, PortID _id)
54 : portName(_name), id(_id), owner(_owner)
55{
56}
57
58Port::~Port()
59{
60}
61
62/**
63 * Master port
64 */
65MasterPort::MasterPort(const std::string& name, MemObject* owner, PortID _id)
66 : Port(name, *owner, _id), _slavePort(NULL)
67{
68}
69
70MasterPort::~MasterPort()
71{
72}
73
74SlavePort&
75MasterPort::getSlavePort() const
76{
77 if(_slavePort == NULL)
78 panic("Cannot getSlavePort on master port %s that is not connected\n",
79 name());
80
81 return *_slavePort;
82}
83
84void
|
85MasterPort::bind(SlavePort& slave_port)
86{
87 // master port keeps track of the slave port
88 _slavePort = &slave_port;
89
90 // slave port also keeps track of master port
91 _slavePort->bind(*this);
92}
93
94bool
95MasterPort::isConnected() const
96{
97 return _slavePort != NULL;
98}
99
100unsigned
101MasterPort::peerBlockSize() const
102{
103 return _slavePort->deviceBlockSize();
104}
105
106AddrRangeList
107MasterPort::getAddrRanges() const
108{
109 return _slavePort->getAddrRanges();
110}
111
112Tick
113MasterPort::sendAtomic(PacketPtr pkt)
114{
115 assert(pkt->isRequest());
116 return _slavePort->recvAtomic(pkt);
117}
118
119void
120MasterPort::sendFunctional(PacketPtr pkt)
121{
122 assert(pkt->isRequest());
123 return _slavePort->recvFunctional(pkt);
124}
125
126bool
127MasterPort::sendTimingReq(PacketPtr pkt)
128{
129 assert(pkt->isRequest());
130 return _slavePort->recvTimingReq(pkt);
131}
132
133bool
134MasterPort::sendTimingSnoopResp(PacketPtr pkt)
135{
136 assert(pkt->isResponse());
137 return _slavePort->recvTimingSnoopResp(pkt);
138}
139
140void
141MasterPort::sendRetry()
142{
143 _slavePort->recvRetry();
144}
145
146void
147MasterPort::printAddr(Addr a)
148{
149 Request req(a, 1, 0, Request::funcMasterId);
150 Packet pkt(&req, MemCmd::PrintReq);
151 Packet::PrintReqState prs(std::cerr);
152 pkt.senderState = &prs;
153
154 sendFunctional(&pkt);
155}
156
157/**
158 * Slave port
159 */
160SlavePort::SlavePort(const std::string& name, MemObject* owner, PortID id)
161 : Port(name, *owner, id), _masterPort(NULL)
162{
163}
164
165SlavePort::~SlavePort()
166{
167}
168
169void
| 91MasterPort::bind(SlavePort& slave_port)
92{
93 // master port keeps track of the slave port
94 _slavePort = &slave_port;
95
96 // slave port also keeps track of master port
97 _slavePort->bind(*this);
98}
99
100bool
101MasterPort::isConnected() const
102{
103 return _slavePort != NULL;
104}
105
106unsigned
107MasterPort::peerBlockSize() const
108{
109 return _slavePort->deviceBlockSize();
110}
111
112AddrRangeList
113MasterPort::getAddrRanges() const
114{
115 return _slavePort->getAddrRanges();
116}
117
118Tick
119MasterPort::sendAtomic(PacketPtr pkt)
120{
121 assert(pkt->isRequest());
122 return _slavePort->recvAtomic(pkt);
123}
124
125void
126MasterPort::sendFunctional(PacketPtr pkt)
127{
128 assert(pkt->isRequest());
129 return _slavePort->recvFunctional(pkt);
130}
131
132bool
133MasterPort::sendTimingReq(PacketPtr pkt)
134{
135 assert(pkt->isRequest());
136 return _slavePort->recvTimingReq(pkt);
137}
138
139bool
140MasterPort::sendTimingSnoopResp(PacketPtr pkt)
141{
142 assert(pkt->isResponse());
143 return _slavePort->recvTimingSnoopResp(pkt);
144}
145
146void
147MasterPort::sendRetry()
148{
149 _slavePort->recvRetry();
150}
151
152void
153MasterPort::printAddr(Addr a)
154{
155 Request req(a, 1, 0, Request::funcMasterId);
156 Packet pkt(&req, MemCmd::PrintReq);
157 Packet::PrintReqState prs(std::cerr);
158 pkt.senderState = &prs;
159
160 sendFunctional(&pkt);
161}
162
163/**
164 * Slave port
165 */
166SlavePort::SlavePort(const std::string& name, MemObject* owner, PortID id)
167 : Port(name, *owner, id), _masterPort(NULL)
168{
169}
170
171SlavePort::~SlavePort()
172{
173}
174
175void
|