1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "base/trace.hh"
50#include "mem/mem_object.hh"
51#include "mem/port.hh"
52
53Port::Port(const std::string &_name, MemObject& _owner)
54 : portName(_name), peer(NULL), owner(_owner)
55{
56}
57
58Port::~Port()
59{
60}
61
62/**
63 * Master port
64 */
65MasterPort::MasterPort(const std::string& name, MemObject* owner)
66 : Port(name, *owner), _slavePort(NULL)
67{
68}
69
70MasterPort::~MasterPort()
71{
72}
73
74SlavePort&
75MasterPort::getSlavePort() const
76{
77 if(_slavePort == NULL)
78 panic("Cannot getSlavePort on master port %s that is not connected\n",
79 name());
80
81 return *_slavePort;
82}
83
84void
85MasterPort::bind(SlavePort& slave_port)
86{
87 // master port keeps track of the slave port
88 _slavePort = &slave_port;
89 peer = &slave_port;
90
91 // slave port also keeps track of master port
92 _slavePort->bind(*this);
93}
94
95bool
96MasterPort::isConnected() const
97{
98 return _slavePort != NULL;
99}
100
101unsigned
102MasterPort::peerBlockSize() const
103{
104 return _slavePort->deviceBlockSize();
105}
106
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "base/trace.hh"
50#include "mem/mem_object.hh"
51#include "mem/port.hh"
52
53Port::Port(const std::string &_name, MemObject& _owner)
54 : portName(_name), peer(NULL), owner(_owner)
55{
56}
57
58Port::~Port()
59{
60}
61
62/**
63 * Master port
64 */
65MasterPort::MasterPort(const std::string& name, MemObject* owner)
66 : Port(name, *owner), _slavePort(NULL)
67{
68}
69
70MasterPort::~MasterPort()
71{
72}
73
74SlavePort&
75MasterPort::getSlavePort() const
76{
77 if(_slavePort == NULL)
78 panic("Cannot getSlavePort on master port %s that is not connected\n",
79 name());
80
81 return *_slavePort;
82}
83
84void
85MasterPort::bind(SlavePort& slave_port)
86{
87 // master port keeps track of the slave port
88 _slavePort = &slave_port;
89 peer = &slave_port;
90
91 // slave port also keeps track of master port
92 _slavePort->bind(*this);
93}
94
95bool
96MasterPort::isConnected() const
97{
98 return _slavePort != NULL;
99}
100
101unsigned
102MasterPort::peerBlockSize() const
103{
104 return _slavePort->deviceBlockSize();
105}
106
|
108MasterPort::printAddr(Addr a)
109{
110 Request req(a, 1, 0, Request::funcMasterId);
111 Packet pkt(&req, MemCmd::PrintReq, Packet::Broadcast);
112 Packet::PrintReqState prs(std::cerr);
113 pkt.senderState = &prs;
114
115 sendFunctional(&pkt);
116}
117
118/**
119 * Slave port
120 */
121SlavePort::SlavePort(const std::string& name, MemObject* owner)
122 : Port(name, *owner), _masterPort(NULL)
123{
124}
125
126SlavePort::~SlavePort()
127{
128}
129
130void
131SlavePort::bind(MasterPort& master_port)
132{
133 _masterPort = &master_port;
134 peer = &master_port;
135}
136
137MasterPort&
138SlavePort::getMasterPort() const
139{
140 if (_masterPort == NULL)
141 panic("Cannot getMasterPort on slave port %s that is not connected\n",
142 name());
143
144 return *_masterPort;
145}
146
147unsigned
148SlavePort::peerBlockSize() const
149{
150 return _masterPort->deviceBlockSize();
151}
152
153bool
154SlavePort::isConnected() const
155{
156 return _masterPort != NULL;
157}
| 120MasterPort::printAddr(Addr a)
121{
122 Request req(a, 1, 0, Request::funcMasterId);
123 Packet pkt(&req, MemCmd::PrintReq, Packet::Broadcast);
124 Packet::PrintReqState prs(std::cerr);
125 pkt.senderState = &prs;
126
127 sendFunctional(&pkt);
128}
129
130/**
131 * Slave port
132 */
133SlavePort::SlavePort(const std::string& name, MemObject* owner)
134 : Port(name, *owner), _masterPort(NULL)
135{
136}
137
138SlavePort::~SlavePort()
139{
140}
141
142void
143SlavePort::bind(MasterPort& master_port)
144{
145 _masterPort = &master_port;
146 peer = &master_port;
147}
148
149MasterPort&
150SlavePort::getMasterPort() const
151{
152 if (_masterPort == NULL)
153 panic("Cannot getMasterPort on slave port %s that is not connected\n",
154 name());
155
156 return *_masterPort;
157}
158
159unsigned
160SlavePort::peerBlockSize() const
161{
162 return _masterPort->deviceBlockSize();
163}
164
165bool
166SlavePort::isConnected() const
167{
168 return _masterPort != NULL;
169}
|