1/*
2 * Copyright (c) 2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "mem/port.hh"
50
51#include "base/trace.hh"
52#include "sim/sim_object.hh"
53
54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
55 : Port(name, _id), _baseSlavePort(NULL)
56{
57}
58
59BaseMasterPort::~BaseMasterPort()
60{
61}
62
63BaseSlavePort&
64BaseMasterPort::getSlavePort() const
65{
66 if (_baseSlavePort == NULL)
67 panic("Cannot getSlavePort on master port %s that is not connected\n",
68 name());
69
70 return *_baseSlavePort;
71}
72
| 1/*
2 * Copyright (c) 2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "mem/port.hh"
50
51#include "base/trace.hh"
52#include "sim/sim_object.hh"
53
54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
55 : Port(name, _id), _baseSlavePort(NULL)
56{
57}
58
59BaseMasterPort::~BaseMasterPort()
60{
61}
62
63BaseSlavePort&
64BaseMasterPort::getSlavePort() const
65{
66 if (_baseSlavePort == NULL)
67 panic("Cannot getSlavePort on master port %s that is not connected\n",
68 name());
69
70 return *_baseSlavePort;
71}
72
|
| 73void
74BaseMasterPort::bind(Port &peer)
75{
76 _baseSlavePort = dynamic_cast<BaseSlavePort *>(&peer);
77 fatal_if(!_baseSlavePort, "Attempt to bind port %s to non-master port %s.",
78 name(), peer.name());
79 Port::bind(peer);
80}
81
82void
83BaseMasterPort::unbind()
84{
85 _baseSlavePort = nullptr;
86 Port::unbind();
87}
88
|
73BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
74 : Port(name, _id), _baseMasterPort(NULL)
75{
76}
77
78BaseSlavePort::~BaseSlavePort()
79{
80}
81
82BaseMasterPort&
83BaseSlavePort::getMasterPort() const
84{
85 if (_baseMasterPort == NULL)
86 panic("Cannot getMasterPort on slave port %s that is not connected\n",
87 name());
88
89 return *_baseMasterPort;
90}
91
| 89BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
90 : Port(name, _id), _baseMasterPort(NULL)
91{
92}
93
94BaseSlavePort::~BaseSlavePort()
95{
96}
97
98BaseMasterPort&
99BaseSlavePort::getMasterPort() const
100{
101 if (_baseMasterPort == NULL)
102 panic("Cannot getMasterPort on slave port %s that is not connected\n",
103 name());
104
105 return *_baseMasterPort;
106}
107
|
| 108void
109BaseSlavePort::bind(Port &peer)
110{
111 _baseMasterPort = dynamic_cast<BaseMasterPort *>(&peer);
112 fatal_if(!_baseMasterPort, "Attempt to bind port %s to non-slave port %s.",
113 name(), peer.name());
114 Port::bind(peer);
115}
116
117void
118BaseSlavePort::unbind()
119{
120 _baseMasterPort = nullptr;
121 Port::unbind();
122}
123
|
92/**
93 * Master port
94 */
95MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
96 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
97{
98}
99
100MasterPort::~MasterPort()
101{
102}
103
104void
105MasterPort::bind(Port &peer)
106{
107 auto *slave_port = dynamic_cast<SlavePort *>(&peer);
108 if (!slave_port) {
109 fatal("Attempt to bind port %s to non-slave port %s.",
110 name(), peer.name());
111 }
| 124/**
125 * Master port
126 */
127MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
128 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
129{
130}
131
132MasterPort::~MasterPort()
133{
134}
135
136void
137MasterPort::bind(Port &peer)
138{
139 auto *slave_port = dynamic_cast<SlavePort *>(&peer);
140 if (!slave_port) {
141 fatal("Attempt to bind port %s to non-slave port %s.",
142 name(), peer.name());
143 }
|
112 // bind on the level of the base ports
113 _baseSlavePort = slave_port;
114
| |
115 // master port keeps track of the slave port
116 _slavePort = slave_port;
| 144 // master port keeps track of the slave port
145 _slavePort = slave_port;
|
117 _connected = true;
| 146 BaseMasterPort::bind(peer);
|
118 // slave port also keeps track of master port
119 _slavePort->slaveBind(*this);
120}
121
122void
123MasterPort::unbind()
124{
125 if (_slavePort == NULL)
126 panic("Attempting to unbind master port %s that is not connected\n",
127 name());
128 _slavePort->slaveUnbind();
| 147 // slave port also keeps track of master port
148 _slavePort->slaveBind(*this);
149}
150
151void
152MasterPort::unbind()
153{
154 if (_slavePort == NULL)
155 panic("Attempting to unbind master port %s that is not connected\n",
156 name());
157 _slavePort->slaveUnbind();
|
129 _slavePort = NULL;
130 _connected = false;
131 _baseSlavePort = NULL;
| 158 _slavePort = nullptr;
159 BaseMasterPort::unbind();
|
132}
133
134AddrRangeList
135MasterPort::getAddrRanges() const
136{
137 return _slavePort->getAddrRanges();
138}
139
140void
141MasterPort::printAddr(Addr a)
142{
143 auto req = std::make_shared<Request>(
144 a, 1, 0, Request::funcMasterId);
145
146 Packet pkt(req, MemCmd::PrintReq);
147 Packet::PrintReqState prs(std::cerr);
148 pkt.senderState = &prs;
149
150 sendFunctional(&pkt);
151}
152
153/**
154 * Slave port
155 */
156SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
157 : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
158 owner(*_owner)
159{
160}
161
162SlavePort::~SlavePort()
163{
164}
165
166void
167SlavePort::slaveUnbind()
168{
| 160}
161
162AddrRangeList
163MasterPort::getAddrRanges() const
164{
165 return _slavePort->getAddrRanges();
166}
167
168void
169MasterPort::printAddr(Addr a)
170{
171 auto req = std::make_shared<Request>(
172 a, 1, 0, Request::funcMasterId);
173
174 Packet pkt(req, MemCmd::PrintReq);
175 Packet::PrintReqState prs(std::cerr);
176 pkt.senderState = &prs;
177
178 sendFunctional(&pkt);
179}
180
181/**
182 * Slave port
183 */
184SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
185 : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
186 owner(*_owner)
187{
188}
189
190SlavePort::~SlavePort()
191{
192}
193
194void
195SlavePort::slaveUnbind()
196{
|
169 _baseMasterPort = NULL;
| |
170 _masterPort = NULL;
| 197 _masterPort = NULL;
|
171 _connected = false;
| 198 BaseSlavePort::unbind();
|
172}
173
174void
175SlavePort::slaveBind(MasterPort& master_port)
176{
| 199}
200
201void
202SlavePort::slaveBind(MasterPort& master_port)
203{
|
177 _baseMasterPort = &master_port;
| |
178 _masterPort = &master_port;
| 204 _masterPort = &master_port;
|
179 _connected = true;
| 205 BaseSlavePort::bind(master_port);
|
180}
181
182Tick
183SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
184{
185 if (!defaultBackdoorWarned) {
186 warn("Port %s doesn't support requesting a back door.", name());
187 defaultBackdoorWarned = true;
188 }
189 return recvAtomic(pkt);
190}
| 206}
207
208Tick
209SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
210{
211 if (!defaultBackdoorWarned) {
212 warn("Port %s doesn't support requesting a back door.", name());
213 defaultBackdoorWarned = true;
214 }
215 return recvAtomic(pkt);
216}
|