1/*
2 * Copyright (c) 2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "mem/port.hh"
50
51#include "base/trace.hh"
| 1/*
2 * Copyright (c) 2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "mem/port.hh"
50
51#include "base/trace.hh"
|
52#include "mem/mem_object.hh"
| 52#include "sim/sim_object.hh"
|
53
54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
55 : Port(name, _id), _baseSlavePort(NULL)
56{
57}
58
59BaseMasterPort::~BaseMasterPort()
60{
61}
62
63BaseSlavePort&
64BaseMasterPort::getSlavePort() const
65{
66 if (_baseSlavePort == NULL)
67 panic("Cannot getSlavePort on master port %s that is not connected\n",
68 name());
69
70 return *_baseSlavePort;
71}
72
73BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
74 : Port(name, _id), _baseMasterPort(NULL)
75{
76}
77
78BaseSlavePort::~BaseSlavePort()
79{
80}
81
82BaseMasterPort&
83BaseSlavePort::getMasterPort() const
84{
85 if (_baseMasterPort == NULL)
86 panic("Cannot getMasterPort on slave port %s that is not connected\n",
87 name());
88
89 return *_baseMasterPort;
90}
91
92/**
93 * Master port
94 */
| 53
54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
55 : Port(name, _id), _baseSlavePort(NULL)
56{
57}
58
59BaseMasterPort::~BaseMasterPort()
60{
61}
62
63BaseSlavePort&
64BaseMasterPort::getSlavePort() const
65{
66 if (_baseSlavePort == NULL)
67 panic("Cannot getSlavePort on master port %s that is not connected\n",
68 name());
69
70 return *_baseSlavePort;
71}
72
73BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
74 : Port(name, _id), _baseMasterPort(NULL)
75{
76}
77
78BaseSlavePort::~BaseSlavePort()
79{
80}
81
82BaseMasterPort&
83BaseSlavePort::getMasterPort() const
84{
85 if (_baseMasterPort == NULL)
86 panic("Cannot getMasterPort on slave port %s that is not connected\n",
87 name());
88
89 return *_baseMasterPort;
90}
91
92/**
93 * Master port
94 */
|
95MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id)
| 95MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
|
96 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
97{
98}
99
100MasterPort::~MasterPort()
101{
102}
103
104void
105MasterPort::bind(Port &peer)
106{
107 auto *slave_port = dynamic_cast<SlavePort *>(&peer);
108 if (!slave_port) {
109 fatal("Attempt to bind port %s to non-slave port %s.",
110 name(), peer.name());
111 }
112 // bind on the level of the base ports
113 _baseSlavePort = slave_port;
114
115 // master port keeps track of the slave port
116 _slavePort = slave_port;
117 _connected = true;
118 // slave port also keeps track of master port
119 _slavePort->slaveBind(*this);
120}
121
122void
123MasterPort::unbind()
124{
125 if (_slavePort == NULL)
126 panic("Attempting to unbind master port %s that is not connected\n",
127 name());
128 _slavePort->slaveUnbind();
129 _slavePort = NULL;
130 _connected = false;
131 _baseSlavePort = NULL;
132}
133
134AddrRangeList
135MasterPort::getAddrRanges() const
136{
137 return _slavePort->getAddrRanges();
138}
139
140Tick
141MasterPort::sendAtomic(PacketPtr pkt)
142{
143 assert(pkt->isRequest());
144 return _slavePort->recvAtomic(pkt);
145}
146
147Tick
148MasterPort::sendAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
149{
150 assert(pkt->isRequest());
151 return _slavePort->recvAtomicBackdoor(pkt, backdoor);
152}
153
154void
155MasterPort::sendFunctional(PacketPtr pkt)
156{
157 assert(pkt->isRequest());
158 return _slavePort->recvFunctional(pkt);
159}
160
161bool
162MasterPort::sendTimingReq(PacketPtr pkt)
163{
164 assert(pkt->isRequest());
165 return _slavePort->recvTimingReq(pkt);
166}
167
168bool
169MasterPort::tryTiming(PacketPtr pkt) const
170{
171 assert(pkt->isRequest());
172 return _slavePort->tryTiming(pkt);
173}
174
175bool
176MasterPort::sendTimingSnoopResp(PacketPtr pkt)
177{
178 assert(pkt->isResponse());
179 return _slavePort->recvTimingSnoopResp(pkt);
180}
181
182void
183MasterPort::sendRetryResp()
184{
185 _slavePort->recvRespRetry();
186}
187
188void
189MasterPort::printAddr(Addr a)
190{
191 auto req = std::make_shared<Request>(
192 a, 1, 0, Request::funcMasterId);
193
194 Packet pkt(req, MemCmd::PrintReq);
195 Packet::PrintReqState prs(std::cerr);
196 pkt.senderState = &prs;
197
198 sendFunctional(&pkt);
199}
200
201/**
202 * Slave port
203 */
| 96 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
97{
98}
99
100MasterPort::~MasterPort()
101{
102}
103
104void
105MasterPort::bind(Port &peer)
106{
107 auto *slave_port = dynamic_cast<SlavePort *>(&peer);
108 if (!slave_port) {
109 fatal("Attempt to bind port %s to non-slave port %s.",
110 name(), peer.name());
111 }
112 // bind on the level of the base ports
113 _baseSlavePort = slave_port;
114
115 // master port keeps track of the slave port
116 _slavePort = slave_port;
117 _connected = true;
118 // slave port also keeps track of master port
119 _slavePort->slaveBind(*this);
120}
121
122void
123MasterPort::unbind()
124{
125 if (_slavePort == NULL)
126 panic("Attempting to unbind master port %s that is not connected\n",
127 name());
128 _slavePort->slaveUnbind();
129 _slavePort = NULL;
130 _connected = false;
131 _baseSlavePort = NULL;
132}
133
134AddrRangeList
135MasterPort::getAddrRanges() const
136{
137 return _slavePort->getAddrRanges();
138}
139
140Tick
141MasterPort::sendAtomic(PacketPtr pkt)
142{
143 assert(pkt->isRequest());
144 return _slavePort->recvAtomic(pkt);
145}
146
147Tick
148MasterPort::sendAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
149{
150 assert(pkt->isRequest());
151 return _slavePort->recvAtomicBackdoor(pkt, backdoor);
152}
153
154void
155MasterPort::sendFunctional(PacketPtr pkt)
156{
157 assert(pkt->isRequest());
158 return _slavePort->recvFunctional(pkt);
159}
160
161bool
162MasterPort::sendTimingReq(PacketPtr pkt)
163{
164 assert(pkt->isRequest());
165 return _slavePort->recvTimingReq(pkt);
166}
167
168bool
169MasterPort::tryTiming(PacketPtr pkt) const
170{
171 assert(pkt->isRequest());
172 return _slavePort->tryTiming(pkt);
173}
174
175bool
176MasterPort::sendTimingSnoopResp(PacketPtr pkt)
177{
178 assert(pkt->isResponse());
179 return _slavePort->recvTimingSnoopResp(pkt);
180}
181
182void
183MasterPort::sendRetryResp()
184{
185 _slavePort->recvRespRetry();
186}
187
188void
189MasterPort::printAddr(Addr a)
190{
191 auto req = std::make_shared<Request>(
192 a, 1, 0, Request::funcMasterId);
193
194 Packet pkt(req, MemCmd::PrintReq);
195 Packet::PrintReqState prs(std::cerr);
196 pkt.senderState = &prs;
197
198 sendFunctional(&pkt);
199}
200
201/**
202 * Slave port
203 */
|
204SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id)
| 204SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
|
205 : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
206 owner(*_owner)
207{
208}
209
210SlavePort::~SlavePort()
211{
212}
213
214void
215SlavePort::slaveUnbind()
216{
217 _baseMasterPort = NULL;
218 _masterPort = NULL;
219 _connected = false;
220}
221
222void
223SlavePort::slaveBind(MasterPort& master_port)
224{
225 _baseMasterPort = &master_port;
226 _masterPort = &master_port;
227 _connected = true;
228}
229
230Tick
231SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
232{
233 if (!defaultBackdoorWarned) {
234 warn("Port %s doesn't support requesting a back door.", name());
235 defaultBackdoorWarned = true;
236 }
237 return recvAtomic(pkt);
238}
239
240Tick
241SlavePort::sendAtomicSnoop(PacketPtr pkt)
242{
243 assert(pkt->isRequest());
244 return _masterPort->recvAtomicSnoop(pkt);
245}
246
247void
248SlavePort::sendFunctionalSnoop(PacketPtr pkt)
249{
250 assert(pkt->isRequest());
251 return _masterPort->recvFunctionalSnoop(pkt);
252}
253
254bool
255SlavePort::sendTimingResp(PacketPtr pkt)
256{
257 assert(pkt->isResponse());
258 return _masterPort->recvTimingResp(pkt);
259}
260
261void
262SlavePort::sendTimingSnoopReq(PacketPtr pkt)
263{
264 assert(pkt->isRequest());
265 _masterPort->recvTimingSnoopReq(pkt);
266}
267
268void
269SlavePort::sendRetryReq()
270{
271 _masterPort->recvReqRetry();
272}
273
274void
275SlavePort::sendRetrySnoopResp()
276{
277 _masterPort->recvRetrySnoopResp();
278}
| 205 : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
206 owner(*_owner)
207{
208}
209
210SlavePort::~SlavePort()
211{
212}
213
214void
215SlavePort::slaveUnbind()
216{
217 _baseMasterPort = NULL;
218 _masterPort = NULL;
219 _connected = false;
220}
221
222void
223SlavePort::slaveBind(MasterPort& master_port)
224{
225 _baseMasterPort = &master_port;
226 _masterPort = &master_port;
227 _connected = true;
228}
229
230Tick
231SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
232{
233 if (!defaultBackdoorWarned) {
234 warn("Port %s doesn't support requesting a back door.", name());
235 defaultBackdoorWarned = true;
236 }
237 return recvAtomic(pkt);
238}
239
240Tick
241SlavePort::sendAtomicSnoop(PacketPtr pkt)
242{
243 assert(pkt->isRequest());
244 return _masterPort->recvAtomicSnoop(pkt);
245}
246
247void
248SlavePort::sendFunctionalSnoop(PacketPtr pkt)
249{
250 assert(pkt->isRequest());
251 return _masterPort->recvFunctionalSnoop(pkt);
252}
253
254bool
255SlavePort::sendTimingResp(PacketPtr pkt)
256{
257 assert(pkt->isResponse());
258 return _masterPort->recvTimingResp(pkt);
259}
260
261void
262SlavePort::sendTimingSnoopReq(PacketPtr pkt)
263{
264 assert(pkt->isRequest());
265 _masterPort->recvTimingSnoopReq(pkt);
266}
267
268void
269SlavePort::sendRetryReq()
270{
271 _masterPort->recvReqRetry();
272}
273
274void
275SlavePort::sendRetrySnoopResp()
276{
277 _masterPort->recvRetrySnoopResp();
278}
|