1/*
2 * Copyright (c) 2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "mem/port.hh"
50
51#include "base/trace.hh"
52#include "mem/mem_object.hh"
53
54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
55 : Port(name, _id), _baseSlavePort(NULL)
56{
57}
58
59BaseMasterPort::~BaseMasterPort()
60{
61}
62
63BaseSlavePort&
64BaseMasterPort::getSlavePort() const
65{
66 if (_baseSlavePort == NULL)
67 panic("Cannot getSlavePort on master port %s that is not connected\n",
68 name());
69
70 return *_baseSlavePort;
71}
72
| 1/*
2 * Copyright (c) 2012,2015,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 * Andreas Hansson
42 * William Wang
43 */
44
45/**
46 * @file
47 * Port object definitions.
48 */
49#include "mem/port.hh"
50
51#include "base/trace.hh"
52#include "mem/mem_object.hh"
53
54BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
55 : Port(name, _id), _baseSlavePort(NULL)
56{
57}
58
59BaseMasterPort::~BaseMasterPort()
60{
61}
62
63BaseSlavePort&
64BaseMasterPort::getSlavePort() const
65{
66 if (_baseSlavePort == NULL)
67 panic("Cannot getSlavePort on master port %s that is not connected\n",
68 name());
69
70 return *_baseSlavePort;
71}
72
|
73bool
74BaseMasterPort::isConnected() const
75{
76 return _baseSlavePort != NULL;
77}
78
| |
79BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
80 : Port(name, _id), _baseMasterPort(NULL)
81{
82}
83
84BaseSlavePort::~BaseSlavePort()
85{
86}
87
88BaseMasterPort&
89BaseSlavePort::getMasterPort() const
90{
91 if (_baseMasterPort == NULL)
92 panic("Cannot getMasterPort on slave port %s that is not connected\n",
93 name());
94
95 return *_baseMasterPort;
96}
97
| 73BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
74 : Port(name, _id), _baseMasterPort(NULL)
75{
76}
77
78BaseSlavePort::~BaseSlavePort()
79{
80}
81
82BaseMasterPort&
83BaseSlavePort::getMasterPort() const
84{
85 if (_baseMasterPort == NULL)
86 panic("Cannot getMasterPort on slave port %s that is not connected\n",
87 name());
88
89 return *_baseMasterPort;
90}
91
|
98bool
99BaseSlavePort::isConnected() const
100{
101 return _baseMasterPort != NULL;
102}
103
| |
104/**
105 * Master port
106 */
107MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id)
108 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
109{
110}
111
112MasterPort::~MasterPort()
113{
114}
115
116void
| 92/**
93 * Master port
94 */
95MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id)
96 : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
97{
98}
99
100MasterPort::~MasterPort()
101{
102}
103
104void
|
117MasterPort::bind(BaseSlavePort& slave_port)
| 105MasterPort::bind(Port &peer)
|
118{
| 106{
|
| 107 auto *slave_port = dynamic_cast<SlavePort *>(&peer);
108 if (!slave_port) {
109 fatal("Attempt to bind port %s to non-slave port %s.",
110 name(), peer.name());
111 }
|
119 // bind on the level of the base ports
| 112 // bind on the level of the base ports
|
120 _baseSlavePort = &slave_port;
| 113 _baseSlavePort = slave_port;
|
121
| 114
|
122 // also attempt to base the slave to the appropriate type
123 SlavePort* cast_slave_port = dynamic_cast<SlavePort*>(&slave_port);
124
125 // if this port is compatible, then proceed with the binding
126 if (cast_slave_port != NULL) {
127 // master port keeps track of the slave port
128 _slavePort = cast_slave_port;
129 // slave port also keeps track of master port
130 _slavePort->bind(*this);
131 } else {
132 fatal("Master port %s cannot bind to %s\n", name(),
133 slave_port.name());
134 }
| 115 // master port keeps track of the slave port
116 _slavePort = slave_port;
117 _connected = true;
118 // slave port also keeps track of master port
119 _slavePort->slaveBind(*this);
|
135}
136
137void
138MasterPort::unbind()
139{
140 if (_slavePort == NULL)
141 panic("Attempting to unbind master port %s that is not connected\n",
142 name());
| 120}
121
122void
123MasterPort::unbind()
124{
125 if (_slavePort == NULL)
126 panic("Attempting to unbind master port %s that is not connected\n",
127 name());
|
143 _slavePort->unbind();
| 128 _slavePort->slaveUnbind();
|
144 _slavePort = NULL;
| 129 _slavePort = NULL;
|
| 130 _connected = false;
|
145 _baseSlavePort = NULL;
146}
147
148AddrRangeList
149MasterPort::getAddrRanges() const
150{
151 return _slavePort->getAddrRanges();
152}
153
154Tick
155MasterPort::sendAtomic(PacketPtr pkt)
156{
157 assert(pkt->isRequest());
158 return _slavePort->recvAtomic(pkt);
159}
160
161void
162MasterPort::sendFunctional(PacketPtr pkt)
163{
164 assert(pkt->isRequest());
165 return _slavePort->recvFunctional(pkt);
166}
167
168bool
169MasterPort::sendTimingReq(PacketPtr pkt)
170{
171 assert(pkt->isRequest());
172 return _slavePort->recvTimingReq(pkt);
173}
174
175bool
176MasterPort::tryTiming(PacketPtr pkt) const
177{
178 assert(pkt->isRequest());
179 return _slavePort->tryTiming(pkt);
180}
181
182bool
183MasterPort::sendTimingSnoopResp(PacketPtr pkt)
184{
185 assert(pkt->isResponse());
186 return _slavePort->recvTimingSnoopResp(pkt);
187}
188
189void
190MasterPort::sendRetryResp()
191{
192 _slavePort->recvRespRetry();
193}
194
195void
196MasterPort::printAddr(Addr a)
197{
198 auto req = std::make_shared<Request>(
199 a, 1, 0, Request::funcMasterId);
200
201 Packet pkt(req, MemCmd::PrintReq);
202 Packet::PrintReqState prs(std::cerr);
203 pkt.senderState = &prs;
204
205 sendFunctional(&pkt);
206}
207
208/**
209 * Slave port
210 */
211SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id)
212 : BaseSlavePort(name, id), _masterPort(NULL), owner(*_owner)
213{
214}
215
216SlavePort::~SlavePort()
217{
218}
219
220void
| 131 _baseSlavePort = NULL;
132}
133
134AddrRangeList
135MasterPort::getAddrRanges() const
136{
137 return _slavePort->getAddrRanges();
138}
139
140Tick
141MasterPort::sendAtomic(PacketPtr pkt)
142{
143 assert(pkt->isRequest());
144 return _slavePort->recvAtomic(pkt);
145}
146
147void
148MasterPort::sendFunctional(PacketPtr pkt)
149{
150 assert(pkt->isRequest());
151 return _slavePort->recvFunctional(pkt);
152}
153
154bool
155MasterPort::sendTimingReq(PacketPtr pkt)
156{
157 assert(pkt->isRequest());
158 return _slavePort->recvTimingReq(pkt);
159}
160
161bool
162MasterPort::tryTiming(PacketPtr pkt) const
163{
164 assert(pkt->isRequest());
165 return _slavePort->tryTiming(pkt);
166}
167
168bool
169MasterPort::sendTimingSnoopResp(PacketPtr pkt)
170{
171 assert(pkt->isResponse());
172 return _slavePort->recvTimingSnoopResp(pkt);
173}
174
175void
176MasterPort::sendRetryResp()
177{
178 _slavePort->recvRespRetry();
179}
180
181void
182MasterPort::printAddr(Addr a)
183{
184 auto req = std::make_shared<Request>(
185 a, 1, 0, Request::funcMasterId);
186
187 Packet pkt(req, MemCmd::PrintReq);
188 Packet::PrintReqState prs(std::cerr);
189 pkt.senderState = &prs;
190
191 sendFunctional(&pkt);
192}
193
194/**
195 * Slave port
196 */
197SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id)
198 : BaseSlavePort(name, id), _masterPort(NULL), owner(*_owner)
199{
200}
201
202SlavePort::~SlavePort()
203{
204}
205
206void
|
221SlavePort::unbind()
| 207SlavePort::slaveUnbind()
|
222{
223 _baseMasterPort = NULL;
224 _masterPort = NULL;
| 208{
209 _baseMasterPort = NULL;
210 _masterPort = NULL;
|
| 211 _connected = false;
|
225}
226
227void
| 212}
213
214void
|
228SlavePort::bind(MasterPort& master_port)
| 215SlavePort::slaveBind(MasterPort& master_port)
|
229{
230 _baseMasterPort = &master_port;
231 _masterPort = &master_port;
| 216{
217 _baseMasterPort = &master_port;
218 _masterPort = &master_port;
|
| 219 _connected = true;
|
232}
233
234Tick
235SlavePort::sendAtomicSnoop(PacketPtr pkt)
236{
237 assert(pkt->isRequest());
238 return _masterPort->recvAtomicSnoop(pkt);
239}
240
241void
242SlavePort::sendFunctionalSnoop(PacketPtr pkt)
243{
244 assert(pkt->isRequest());
245 return _masterPort->recvFunctionalSnoop(pkt);
246}
247
248bool
249SlavePort::sendTimingResp(PacketPtr pkt)
250{
251 assert(pkt->isResponse());
252 return _masterPort->recvTimingResp(pkt);
253}
254
255void
256SlavePort::sendTimingSnoopReq(PacketPtr pkt)
257{
258 assert(pkt->isRequest());
259 _masterPort->recvTimingSnoopReq(pkt);
260}
261
262void
263SlavePort::sendRetryReq()
264{
265 _masterPort->recvReqRetry();
266}
267
268void
269SlavePort::sendRetrySnoopResp()
270{
271 _masterPort->recvRetrySnoopResp();
272}
| 220}
221
222Tick
223SlavePort::sendAtomicSnoop(PacketPtr pkt)
224{
225 assert(pkt->isRequest());
226 return _masterPort->recvAtomicSnoop(pkt);
227}
228
229void
230SlavePort::sendFunctionalSnoop(PacketPtr pkt)
231{
232 assert(pkt->isRequest());
233 return _masterPort->recvFunctionalSnoop(pkt);
234}
235
236bool
237SlavePort::sendTimingResp(PacketPtr pkt)
238{
239 assert(pkt->isResponse());
240 return _masterPort->recvTimingResp(pkt);
241}
242
243void
244SlavePort::sendTimingSnoopReq(PacketPtr pkt)
245{
246 assert(pkt->isRequest());
247 _masterPort->recvTimingSnoopReq(pkt);
248}
249
250void
251SlavePort::sendRetryReq()
252{
253 _masterPort->recvReqRetry();
254}
255
256void
257SlavePort::sendRetrySnoopResp()
258{
259 _masterPort->recvRetrySnoopResp();
260}
|