physical.cc (12776:410b60d8a397) physical.cc (12779:c1dc175bb9be)
1/*
2 * Copyright (c) 2012, 2014, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 60 unchanged lines hidden (view full) ---

69#endif
70#endif
71
72using namespace std;
73
74PhysicalMemory::PhysicalMemory(const string& _name,
75 const vector<AbstractMemory*>& _memories,
76 bool mmap_using_noreserve) :
1/*
2 * Copyright (c) 2012, 2014, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 60 unchanged lines hidden (view full) ---

69#endif
70#endif
71
72using namespace std;
73
74PhysicalMemory::PhysicalMemory(const string& _name,
75 const vector<AbstractMemory*>& _memories,
76 bool mmap_using_noreserve) :
77 _name(_name), rangeCache(addrMap.end()), size(0),
78 mmapUsingNoReserve(mmap_using_noreserve)
77 _name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve)
79{
80 if (mmap_using_noreserve)
81 warn("Not reserving swap space. May cause SIGSEGV on actual usage\n");
82
83 // add the memories from the system to the address map as
84 // appropriate
85 for (const auto& m : _memories) {
86 // only add the memory if it is part of the global address map

--- 144 unchanged lines hidden (view full) ---

231 // unmap the backing store
232 for (auto& s : backingStore)
233 munmap((char*)s.pmem, s.range.size());
234}
235
236bool
237PhysicalMemory::isMemAddr(Addr addr) const
238{
78{
79 if (mmap_using_noreserve)
80 warn("Not reserving swap space. May cause SIGSEGV on actual usage\n");
81
82 // add the memories from the system to the address map as
83 // appropriate
84 for (const auto& m : _memories) {
85 // only add the memory if it is part of the global address map

--- 144 unchanged lines hidden (view full) ---

230 // unmap the backing store
231 for (auto& s : backingStore)
232 munmap((char*)s.pmem, s.range.size());
233}
234
235bool
236PhysicalMemory::isMemAddr(Addr addr) const
237{
239 // see if the address is within the last matched range
240 if (rangeCache != addrMap.end() && rangeCache->first.contains(addr)) {
241 return true;
242 } else {
243 // lookup in the interval tree
244 const auto& r = addrMap.contains(addr);
245 if (r == addrMap.end()) {
246 // not in the cache, and not in the tree
247 return false;
248 }
249 // the range is in the tree, update the cache
250 rangeCache = r;
251 return true;
252 }
238 return addrMap.contains(addr) != addrMap.end();
253}
254
255AddrRangeList
256PhysicalMemory::getConfAddrRanges() const
257{
258 // this could be done once in the constructor, but since it is unlikely to
259 // be called more than once the iteration should not be a problem
260 AddrRangeList ranges;

--- 27 unchanged lines hidden (view full) ---

288 return ranges;
289}
290
291void
292PhysicalMemory::access(PacketPtr pkt)
293{
294 assert(pkt->isRequest());
295 Addr addr = pkt->getAddr();
239}
240
241AddrRangeList
242PhysicalMemory::getConfAddrRanges() const
243{
244 // this could be done once in the constructor, but since it is unlikely to
245 // be called more than once the iteration should not be a problem
246 AddrRangeList ranges;

--- 27 unchanged lines hidden (view full) ---

274 return ranges;
275}
276
277void
278PhysicalMemory::access(PacketPtr pkt)
279{
280 assert(pkt->isRequest());
281 Addr addr = pkt->getAddr();
296 if (rangeCache != addrMap.end() && rangeCache->first.contains(addr)) {
297 rangeCache->second->access(pkt);
298 } else {
299 // do not update the cache here, as we typically call
300 // isMemAddr before calling access
301 const auto& m = addrMap.contains(addr);
302 assert(m != addrMap.end());
303 m->second->access(pkt);
304 }
282 const auto& m = addrMap.contains(addr);
283 assert(m != addrMap.end());
284 m->second->access(pkt);
305}
306
307void
308PhysicalMemory::functionalAccess(PacketPtr pkt)
309{
310 assert(pkt->isRequest());
311 Addr addr = pkt->getAddr();
285}
286
287void
288PhysicalMemory::functionalAccess(PacketPtr pkt)
289{
290 assert(pkt->isRequest());
291 Addr addr = pkt->getAddr();
312 if (rangeCache != addrMap.end() && rangeCache->first.contains(addr)) {
313 rangeCache->second->functionalAccess(pkt);
314 } else {
315 // do not update the cache here, as we typically call
316 // isMemAddr before calling functionalAccess
317 const auto& m = addrMap.contains(addr);
318 assert(m != addrMap.end());
319 m->second->functionalAccess(pkt);
320 }
292 const auto& m = addrMap.contains(addr);
293 assert(m != addrMap.end());
294 m->second->functionalAccess(pkt);
321}
322
323void
324PhysicalMemory::serialize(CheckpointOut &cp) const
325{
326 // serialize all the locked addresses and their context ids
327 vector<Addr> lal_addr;
328 vector<ContextID> lal_cid;

--- 154 unchanged lines hidden --- 		295}
296
297void
298PhysicalMemory::serialize(CheckpointOut &cp) const
299{
300 // serialize all the locked addresses and their context ids
301 vector<Addr> lal_addr;
302 vector<ContextID> lal_cid;

--- 154 unchanged lines hidden ---