1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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90 // memories are allowed to overlap in the logic address
91 // map
92 vector<AbstractMemory*> unmapped_mems;
93 unmapped_mems.push_back(*m);
94 createBackingStore((*m)->getAddrRange(), unmapped_mems);
95 }
96 }
97
98 // iterate over the increasing addresses and create as large
99 // chunks as possible of contigous space to be mapped to backing
100 // store, also remember what memories constitute the range so we
101 // can go and find out if we have to init their parts to zero
102 AddrRange curr_range;
103 vector<AbstractMemory*> curr_memories;
104 for (AddrRangeMap<AbstractMemory*>::const_iterator r = addrMap.begin();
105 r != addrMap.end(); ++r) {
106 // simply skip past all memories that are null and hence do
107 // not need any backing store
108 if (!r->second->isNull()) {
109 // if the current range is valid, decide if we split or
110 // not
111 if (curr_range.valid()) {
112 // if the ranges are neighbours, then append, this
113 // will eventually be extended to include support for
114 // address striping and merge the interleaved ranges
115 if (curr_range.end + 1 == r->first.start) {
116 DPRINTF(BusAddrRanges,
117 "Merging neighbouring ranges %x:%x and %x:%x\n",
118 curr_range.start, curr_range.end, r->first.start,
119 r->first.end);
120 // update the end of the range and add the current
121 // memory to the list of memories
122 curr_range.end = r->first.end;
123 curr_memories.push_back(r->second);
124 } else {
125 // what we already have is valid, and this is not
126 // contigious, so create the backing store and
127 // then start over
128 createBackingStore(curr_range, curr_memories);
129
130 // remember the current range and reset the current
131 // set of memories to contain this one
132 curr_range = r->first;
133 curr_memories.clear();
134 curr_memories.push_back(r->second);
135 }
136 } else {
137 // we haven't seen any valid ranges yet, so remember
138 // the current range and reset the current set of
139 // memories to contain this one
140 curr_range = r->first;
141 curr_memories.clear();
142 curr_memories.push_back(r->second);
143 }
144 }
145 }
146
147 // if we have a valid range upon finishing the iteration, then
148 // create the backing store
149 if (curr_range.valid())
150 createBackingStore(curr_range, curr_memories);
151}
152
153void
154PhysicalMemory::createBackingStore(AddrRange range,
155 const vector<AbstractMemory*>& _memories)
156{
157 // perform the actual mmap
158 DPRINTF(BusAddrRanges, "Creating backing store for range %x:%x\n",

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167 fatal("Could not mmap %d bytes for range %x:%x!\n", range.size(),
168 range.start, range.end);
169 }
170
171 // remember this backing store so we can checkpoint it and unmap
172 // it appropriately
173 backingStore.push_back(make_pair(range, pmem));
174
175 // point the memories to their backing store, and if requested,
176 // initialize the memory range to 0
177 for (vector<AbstractMemory*>::const_iterator m = _memories.begin();
178 m != _memories.end(); ++m) {
179 DPRINTF(BusAddrRanges, "Mapping memory %s to backing store\n",
180 (*m)->name());
181 (*m)->setBackingStore(pmem);
182
183 // if it should be zero, then go and make it so
184 if ((*m)->initToZero())
185 memset(pmem, 0, (*m)->size());
186
187 // advance the pointer for the next memory in line
188 pmem += (*m)->size();
189 }
190}
191
192PhysicalMemory::~PhysicalMemory()
193{
194 // unmap the backing store
195 for (vector<pair<AddrRange, uint8_t*> >::iterator s = backingStore.begin();
196 s != backingStore.end(); ++s)

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