page_table.hh (8601:af28085882dc) page_table.hh (8763:509e9bb84dfa)
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#define __MEM_PAGE_TABLE_HH__
38
39#include <string>
40
41#include "arch/isa_traits.hh"
42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#define __MEM_PAGE_TABLE_HH__
38
39#include <string>
40
41#include "arch/isa_traits.hh"
42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
45#include "config/full_system.hh"
45#include "config/the_isa.hh"
46#include "mem/request.hh"
47#include "sim/serialize.hh"
48
46#include "config/the_isa.hh"
47#include "mem/request.hh"
48#include "sim/serialize.hh"
49
50#if !FULL_SYSTEM
51class Process;
52#endif
53
49/**
50 * Page Table Declaration.
51 */
52class PageTable
53{
54 protected:
55 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
56 typedef PTable::iterator PTableItr;

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61 TheISA::TlbEntry entry;
62 };
63
64 struct cacheElement pTableCache[3];
65
66 const Addr pageSize;
67 const Addr offsetMask;
68
54/**
55 * Page Table Declaration.
56 */
57class PageTable
58{
59 protected:
60 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
61 typedef PTable::iterator PTableItr;

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66 TheISA::TlbEntry entry;
67 };
68
69 struct cacheElement pTableCache[3];
70
71 const Addr pageSize;
72 const Addr offsetMask;
73
69 const uint64_t pid;
70 const std::string _name;
74#if !FULL_SYSTEM
75 Process *process;
76#endif
71
72 public:
73
77
78 public:
79
74 PageTable(const std::string &__name, uint64_t _pid,
75 Addr _pageSize = TheISA::VMPageSize);
80 PageTable(
81#if !FULL_SYSTEM
82 Process *_process,
83#endif
84 Addr _pageSize = TheISA::VMPageSize);
76
77 ~PageTable();
78
85
86 ~PageTable();
87
79 // for DPRINTF compatibility
80 const std::string name() const { return _name; }
81
82 Addr pageAlign(Addr a) { return (a & ~offsetMask); }
83 Addr pageOffset(Addr a) { return (a & offsetMask); }
84
88 Addr pageAlign(Addr a) { return (a & ~offsetMask); }
89 Addr pageOffset(Addr a) { return (a & offsetMask); }
90
85 void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
91 void allocate(Addr vaddr, int64_t size);
86 void remap(Addr vaddr, int64_t size, Addr new_vaddr);
92 void remap(Addr vaddr, int64_t size, Addr new_vaddr);
87 void unmap(Addr vaddr, int64_t size);
93 void deallocate(Addr vaddr, int64_t size);
88
89 /**
94
95 /**
90 * Check if any pages in a region are already allocated
91 * @param vaddr The starting virtual address of the region.
92 * @param size The length of the region.
93 * @return True if no pages in the region are mapped.
94 */
95 bool isUnmapped(Addr vaddr, int64_t size);
96
97 /**
98 * Lookup function
99 * @param vaddr The virtual address.
100 * @return entry The page table entry corresponding to vaddr.
101 */
102 bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
103
104 /**
105 * Translate function

--- 42 unchanged lines hidden --- 		96 * Lookup function
97 * @param vaddr The virtual address.
98 * @return entry The page table entry corresponding to vaddr.
99 */
100 bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
101
102 /**
103 * Translate function

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