page_table.hh (10558:426665ec11a9) | page_table.hh (10905:a6ca6831e775) |
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1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2003 The Regents of The University of Michigan 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 39 unchanged lines hidden (view full) --- 48#include "sim/serialize.hh" 49#include "sim/system.hh" 50 51class ThreadContext; 52 53/** 54 * Declaration of base class for page table 55 */ | 1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2003 The Regents of The University of Michigan 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 39 unchanged lines hidden (view full) --- 48#include "sim/serialize.hh" 49#include "sim/system.hh" 50 51class ThreadContext; 52 53/** 54 * Declaration of base class for page table 55 */ |
56class PageTableBase | 56class PageTableBase : public Serializable |
57{ 58 protected: 59 struct cacheElement { 60 bool valid; 61 Addr vaddr; 62 TheISA::TlbEntry entry; 63 }; 64 --- 122 unchanged lines hidden (view full) --- 187 if (pTableCache[0].valid && pTableCache[0].vaddr == vaddr) { 188 pTableCache[0].valid = false; 189 } else if (pTableCache[1].valid && pTableCache[1].vaddr == vaddr) { 190 pTableCache[1].valid = false; 191 } else if (pTableCache[2].valid && pTableCache[2].vaddr == vaddr) { 192 pTableCache[2].valid = false; 193 } 194 } | 57{ 58 protected: 59 struct cacheElement { 60 bool valid; 61 Addr vaddr; 62 TheISA::TlbEntry entry; 63 }; 64 --- 122 unchanged lines hidden (view full) --- 187 if (pTableCache[0].valid && pTableCache[0].vaddr == vaddr) { 188 pTableCache[0].valid = false; 189 } else if (pTableCache[1].valid && pTableCache[1].vaddr == vaddr) { 190 pTableCache[1].valid = false; 191 } else if (pTableCache[2].valid && pTableCache[2].vaddr == vaddr) { 192 pTableCache[2].valid = false; 193 } 194 } |
195 196 virtual void serialize(std::ostream &os) = 0; 197 198 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; | |
199}; 200 201/** 202 * Declaration of functional page table. 203 */ 204class FuncPageTable : public PageTableBase 205{ 206 private: --- 27 unchanged lines hidden (view full) --- 234 235 /** 236 * Lookup function 237 * @param vaddr The virtual address. 238 * @return entry The page table entry corresponding to vaddr. 239 */ 240 bool lookup(Addr vaddr, TheISA::TlbEntry &entry); 241 | 195}; 196 197/** 198 * Declaration of functional page table. 199 */ 200class FuncPageTable : public PageTableBase 201{ 202 private: --- 27 unchanged lines hidden (view full) --- 230 231 /** 232 * Lookup function 233 * @param vaddr The virtual address. 234 * @return entry The page table entry corresponding to vaddr. 235 */ 236 bool lookup(Addr vaddr, TheISA::TlbEntry &entry); 237 |
242 void serialize(std::ostream &os); 243 244 void unserialize(Checkpoint *cp, const std::string §ion); | 238 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 239 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; |
245}; 246 247/** 248 * Faux page table class indended to stop the usage of 249 * an architectural page table, when there is none defined 250 * for a particular ISA. 251 */ 252class NoArchPageTable : public FuncPageTable 253{ 254 public: 255 NoArchPageTable(const std::string &__name, uint64_t _pid, System *_sys, 256 Addr _pageSize = TheISA::PageBytes) : FuncPageTable(__name, _pid) 257 { 258 fatal("No architectural page table defined for this ISA.\n"); 259 } 260}; 261 262#endif // __MEM_PAGE_TABLE_HH__ | 240}; 241 242/** 243 * Faux page table class indended to stop the usage of 244 * an architectural page table, when there is none defined 245 * for a particular ISA. 246 */ 247class NoArchPageTable : public FuncPageTable 248{ 249 public: 250 NoArchPageTable(const std::string &__name, uint64_t _pid, System *_sys, 251 Addr _pageSize = TheISA::PageBytes) : FuncPageTable(__name, _pid) 252 { 253 fatal("No architectural page table defined for this ISA.\n"); 254 } 255}; 256 257#endif // __MEM_PAGE_TABLE_HH__ |