1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 33 unchanged lines hidden (view full) --- 42#include "arch/tlb.hh" 43#include "base/hashmap.hh" 44#include "base/types.hh" 45#include "config/full_system.hh" 46#include "config/the_isa.hh" 47#include "mem/request.hh" 48#include "sim/serialize.hh" 49 |
50class Process; |
51 52/** 53 * Page Table Declaration. 54 */ 55class PageTable 56{ 57 protected: 58 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable; --- 5 unchanged lines hidden (view full) --- 64 TheISA::TlbEntry entry; 65 }; 66 67 struct cacheElement pTableCache[3]; 68 69 const Addr pageSize; 70 const Addr offsetMask; 71 |
72 Process *process; |
73 74 public: 75 |
76 PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize); |
77 78 ~PageTable(); 79 80 Addr pageAlign(Addr a) { return (a & ~offsetMask); } 81 Addr pageOffset(Addr a) { return (a & offsetMask); } 82 83 void allocate(Addr vaddr, int64_t size); 84 void remap(Addr vaddr, int64_t size, Addr new_vaddr); --- 53 unchanged lines hidden --- |