1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41#include "arch/isa_traits.hh"
42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
45#include "config/the_isa.hh"
46#include "mem/request.hh"
47#include "sim/serialize.hh"
48
49class Process;
50
51/**
52 * Page Table Declaration.
53 */
54class PageTable
55{
56 protected:
57 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;
58 typedef PTable::iterator PTableItr;

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63 TheISA::TlbEntry entry;
64 };
65
66 struct cacheElement pTableCache[3];
67
68 const Addr pageSize;
69 const Addr offsetMask;
70
71 Process *process;
72
73 public:
74
75 PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
76
77 ~PageTable();
78
79 Addr pageAlign(Addr a) { return (a & ~offsetMask); }
80 Addr pageOffset(Addr a) { return (a & offsetMask); }
81
82 void allocate(Addr vaddr, int64_t size);
83 void remap(Addr vaddr, int64_t size, Addr new_vaddr);
84 void deallocate(Addr vaddr, int64_t size);
85
86 /**
87 * Lookup function
88 * @param vaddr The virtual address.
89 * @return entry The page table entry corresponding to vaddr.
90 */
91 bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
92
93 /**
94 * Translate function

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