1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42#include "arch/tlb.hh"
43#include "base/hashmap.hh"
44#include "base/types.hh"
45#include "config/full_system.hh"
46#include "config/the_isa.hh"
47#include "mem/request.hh"
48#include "sim/serialize.hh"
49
50#if !FULL_SYSTEM
51class Process;
52#endif
53
54/**
55 * Page Table Declaration.
56 */
57class PageTable
58{
59 protected:
60 typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable;

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66 TheISA::TlbEntry entry;
67 };
68
69 struct cacheElement pTableCache[3];
70
71 const Addr pageSize;
72 const Addr offsetMask;
73
74#if !FULL_SYSTEM
75 Process *process;
76#endif
77
78 public:
79
80 PageTable(
81#if !FULL_SYSTEM
82 Process *_process,
83#endif
84 Addr _pageSize = TheISA::VMPageSize);
85
86 ~PageTable();
87
88 Addr pageAlign(Addr a) { return (a & ~offsetMask); }
89 Addr pageOffset(Addr a) { return (a & offsetMask); }
90
91 void allocate(Addr vaddr, int64_t size);
92 void remap(Addr vaddr, int64_t size, Addr new_vaddr);

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