page_table.cc (8766:b0773af78423) | page_table.cc (8795:0909f8ed7aa0) |
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1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40 41#include "base/bitfield.hh" 42#include "base/intmath.hh" 43#include "base/trace.hh" 44#include "config/the_isa.hh" 45#include "debug/MMU.hh" 46#include "mem/page_table.hh" 47#include "sim/faults.hh" | 1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40 41#include "base/bitfield.hh" 42#include "base/intmath.hh" 43#include "base/trace.hh" 44#include "config/the_isa.hh" 45#include "debug/MMU.hh" 46#include "mem/page_table.hh" 47#include "sim/faults.hh" |
48#include "sim/process.hh" | |
49#include "sim/sim_object.hh" | 48#include "sim/sim_object.hh" |
50#include "sim/system.hh" | |
51 52using namespace std; 53using namespace TheISA; 54 | 49 50using namespace std; 51using namespace TheISA; 52 |
55PageTable::PageTable(Process *_process, Addr _pageSize) | 53PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize) |
56 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), | 54 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), |
57 process(_process) | 55 pid(_pid), _name(__name) |
58{ 59 assert(isPowerOf2(pageSize)); 60 pTableCache[0].vaddr = 0; 61 pTableCache[1].vaddr = 0; 62 pTableCache[2].vaddr = 0; 63} 64 65PageTable::~PageTable() 66{ 67} 68 69void | 56{ 57 assert(isPowerOf2(pageSize)); 58 pTableCache[0].vaddr = 0; 59 pTableCache[1].vaddr = 0; 60 pTableCache[2].vaddr = 0; 61} 62 63PageTable::~PageTable() 64{ 65} 66 67void |
70PageTable::allocate(Addr vaddr, int64_t size) | 68PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber) |
71{ 72 // starting address must be page aligned 73 assert(pageOffset(vaddr) == 0); 74 75 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 76 | 69{ 70 // starting address must be page aligned 71 assert(pageOffset(vaddr) == 0); 72 73 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 74 |
77 for (; size > 0; size -= pageSize, vaddr += pageSize) { 78 PTableItr iter = pTable.find(vaddr); 79 80 if (iter != pTable.end()) { | 75 for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { 76 if (!clobber && (pTable.find(vaddr) != pTable.end())) { |
81 // already mapped | 77 // already mapped |
82 fatal("PageTable::allocate: address 0x%x already mapped", 83 vaddr); | 78 fatal("PageTable::allocate: address 0x%x already mapped", vaddr); |
84 } 85 | 79 } 80 |
86 pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr, 87 process->system->new_page()); | 81 pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr); |
88 updateCache(vaddr, pTable[vaddr]); 89 } 90} 91 92void 93PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 94{ 95 assert(pageOffset(vaddr) == 0); --- 10 unchanged lines hidden (view full) --- 106 pTable[new_vaddr] = pTable[vaddr]; 107 pTable.erase(vaddr); 108 pTable[new_vaddr].updateVaddr(new_vaddr); 109 updateCache(new_vaddr, pTable[new_vaddr]); 110 } 111} 112 113void | 82 updateCache(vaddr, pTable[vaddr]); 83 } 84} 85 86void 87PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 88{ 89 assert(pageOffset(vaddr) == 0); --- 10 unchanged lines hidden (view full) --- 100 pTable[new_vaddr] = pTable[vaddr]; 101 pTable.erase(vaddr); 102 pTable[new_vaddr].updateVaddr(new_vaddr); 103 updateCache(new_vaddr, pTable[new_vaddr]); 104 } 105} 106 107void |
114PageTable::deallocate(Addr vaddr, int64_t size) | 108PageTable::unmap(Addr vaddr, int64_t size) |
115{ 116 assert(pageOffset(vaddr) == 0); 117 | 109{ 110 assert(pageOffset(vaddr) == 0); 111 |
118 DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size); | 112 DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size); |
119 120 for (; size > 0; size -= pageSize, vaddr += pageSize) { 121 PTableItr iter = pTable.find(vaddr); 122 123 assert(iter != pTable.end()); 124 125 pTable.erase(vaddr); 126 } 127 128} 129 130bool | 113 114 for (; size > 0; size -= pageSize, vaddr += pageSize) { 115 PTableItr iter = pTable.find(vaddr); 116 117 assert(iter != pTable.end()); 118 119 pTable.erase(vaddr); 120 } 121 122} 123 124bool |
125PageTable::isUnmapped(Addr vaddr, int64_t size) 126{ 127 // starting address must be page aligned 128 assert(pageOffset(vaddr) == 0); 129 130 for (; size > 0; size -= pageSize, vaddr += pageSize) { 131 if (pTable.find(vaddr) != pTable.end()) { 132 return false; 133 } 134 } 135 136 return true; 137} 138 139bool |
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131PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) 132{ 133 Addr page_addr = pageAlign(vaddr); 134 135 if (pTableCache[0].vaddr == page_addr) { 136 entry = pTableCache[0].entry; 137 return true; 138 } --- 52 unchanged lines hidden (view full) --- 191{ 192 paramOut(os, "ptable.size", pTable.size()); 193 194 PTable::size_type count = 0; 195 196 PTableItr iter = pTable.begin(); 197 PTableItr end = pTable.end(); 198 while (iter != end) { | 140PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) 141{ 142 Addr page_addr = pageAlign(vaddr); 143 144 if (pTableCache[0].vaddr == page_addr) { 145 entry = pTableCache[0].entry; 146 return true; 147 } --- 52 unchanged lines hidden (view full) --- 200{ 201 paramOut(os, "ptable.size", pTable.size()); 202 203 PTable::size_type count = 0; 204 205 PTableItr iter = pTable.begin(); 206 PTableItr end = pTable.end(); 207 while (iter != end) { |
199 os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n"; | 208 os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n"; |
200 201 paramOut(os, "vaddr", iter->first); 202 iter->second.serialize(os); 203 204 ++iter; 205 ++count; 206 } 207 assert(count == pTable.size()); --- 6 unchanged lines hidden (view full) --- 214 paramIn(cp, section, "ptable.size", count); 215 216 pTable.clear(); 217 218 while (i < count) { 219 TheISA::TlbEntry *entry; 220 Addr vaddr; 221 | 209 210 paramOut(os, "vaddr", iter->first); 211 iter->second.serialize(os); 212 213 ++iter; 214 ++count; 215 } 216 assert(count == pTable.size()); --- 6 unchanged lines hidden (view full) --- 223 paramIn(cp, section, "ptable.size", count); 224 225 pTable.clear(); 226 227 while (i < count) { 228 TheISA::TlbEntry *entry; 229 Addr vaddr; 230 |
222 paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr); | 231 paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); |
223 entry = new TheISA::TlbEntry(); | 232 entry = new TheISA::TlbEntry(); |
224 entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); | 233 entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); |
225 pTable[vaddr] = *entry; 226 ++i; 227 } 228} 229 | 234 pTable[vaddr] = *entry; 235 ++i; 236 } 237} 238 |