page_table.cc (8641:4d3ecac1abec) page_table.cc (8763:509e9bb84dfa)
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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40
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "debug/MMU.hh"
46#include "mem/page_table.hh"
47#include "sim/faults.hh"
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 31 unchanged lines hidden (view full) ---

40
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "debug/MMU.hh"
46#include "mem/page_table.hh"
47#include "sim/faults.hh"
48#include "sim/process.hh"
48#include "sim/sim_object.hh"
49#include "sim/sim_object.hh"
50#include "sim/system.hh"
49
50using namespace std;
51using namespace TheISA;
52
51
52using namespace std;
53using namespace TheISA;
54
53PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize)
54 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
55 pid(_pid), _name(__name)
55PageTable::PageTable(
56#if !FULL_SYSTEM
57 Process *_process,
58#endif
59 Addr _pageSize)
60 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize)))
61#if !FULL_SYSTEM
62 , process(_process)
63#endif
56{
57 assert(isPowerOf2(pageSize));
58 pTableCache[0].vaddr = 0;
59 pTableCache[1].vaddr = 0;
60 pTableCache[2].vaddr = 0;
61}
62
63PageTable::~PageTable()
64{
65}
66
67void
64{
65 assert(isPowerOf2(pageSize));
66 pTableCache[0].vaddr = 0;
67 pTableCache[1].vaddr = 0;
68 pTableCache[2].vaddr = 0;
69}
70
71PageTable::~PageTable()
72{
73}
74
75void
68PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
76PageTable::allocate(Addr vaddr, int64_t size)
69{
70 // starting address must be page aligned
71 assert(pageOffset(vaddr) == 0);
72
73 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
74
77{
78 // starting address must be page aligned
79 assert(pageOffset(vaddr) == 0);
80
81 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
82
75 for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
76 if (!clobber && (pTable.find(vaddr) != pTable.end())) {
83 for (; size > 0; size -= pageSize, vaddr += pageSize) {
84 PTableItr iter = pTable.find(vaddr);
85
86 if (iter != pTable.end()) {
77 // already mapped
87 // already mapped
78 fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
88 fatal("PageTable::allocate: address 0x%x already mapped",
89 vaddr);
79 }
80
90 }
91
81 pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
92#if !FULL_SYSTEM
93 pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
94 process->system->new_page());
82 updateCache(vaddr, pTable[vaddr]);
95 updateCache(vaddr, pTable[vaddr]);
96#endif
83 }
84}
85
86void
87PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
88{
89 assert(pageOffset(vaddr) == 0);
90 assert(pageOffset(new_vaddr) == 0);
91
92 DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
93 new_vaddr, size);
94
95 for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
97 }
98}
99
100void
101PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
102{
103 assert(pageOffset(vaddr) == 0);
104 assert(pageOffset(new_vaddr) == 0);
105
106 DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
107 new_vaddr, size);
108
109 for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
96 assert(pTable.find(vaddr) != pTable.end());
110 PTableItr iter = pTable.find(vaddr);
97
111
112 assert(iter != pTable.end());
113
98 pTable[new_vaddr] = pTable[vaddr];
99 pTable.erase(vaddr);
100 pTable[new_vaddr].updateVaddr(new_vaddr);
101 updateCache(new_vaddr, pTable[new_vaddr]);
102 }
103}
104
105void
114 pTable[new_vaddr] = pTable[vaddr];
115 pTable.erase(vaddr);
116 pTable[new_vaddr].updateVaddr(new_vaddr);
117 updateCache(new_vaddr, pTable[new_vaddr]);
118 }
119}
120
121void
106PageTable::unmap(Addr vaddr, int64_t size)
122PageTable::deallocate(Addr vaddr, int64_t size)
107{
108 assert(pageOffset(vaddr) == 0);
109
123{
124 assert(pageOffset(vaddr) == 0);
125
110 DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
126 DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
111
112 for (; size > 0; size -= pageSize, vaddr += pageSize) {
127
128 for (; size > 0; size -= pageSize, vaddr += pageSize) {
113 assert(pTable.find(vaddr) != pTable.end());
129 PTableItr iter = pTable.find(vaddr);
114
130
131 assert(iter != pTable.end());
132
115 pTable.erase(vaddr);
116 }
117
118}
119
120bool
133 pTable.erase(vaddr);
134 }
135
136}
137
138bool
121PageTable::isUnmapped(Addr vaddr, int64_t size)
122{
123 // starting address must be page aligned
124 assert(pageOffset(vaddr) == 0);
125
126 for (; size > 0; size -= pageSize, vaddr += pageSize) {
127 if (pTable.find(vaddr) != pTable.end()) {
128 return false;
129 }
130 }
131
132 return true;
133}
134
135bool
136PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
137{
138 Addr page_addr = pageAlign(vaddr);
139
140 if (pTableCache[0].vaddr == page_addr) {
141 entry = pTableCache[0].entry;
142 return true;
143 }

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196{
197 paramOut(os, "ptable.size", pTable.size());
198
199 PTable::size_type count = 0;
200
201 PTableItr iter = pTable.begin();
202 PTableItr end = pTable.end();
203 while (iter != end) {
139PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
140{
141 Addr page_addr = pageAlign(vaddr);
142
143 if (pTableCache[0].vaddr == page_addr) {
144 entry = pTableCache[0].entry;
145 return true;
146 }

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199{
200 paramOut(os, "ptable.size", pTable.size());
201
202 PTable::size_type count = 0;
203
204 PTableItr iter = pTable.begin();
205 PTableItr end = pTable.end();
206 while (iter != end) {
204 os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
207#if !FULL_SYSTEM
208 os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
209#endif
205
206 paramOut(os, "vaddr", iter->first);
207 iter->second.serialize(os);
208
209 ++iter;
210 ++count;
211 }
212 assert(count == pTable.size());
213}
214
215void
216PageTable::unserialize(Checkpoint *cp, const std::string &section)
217{
218 int i = 0, count;
219 paramIn(cp, section, "ptable.size", count);
210
211 paramOut(os, "vaddr", iter->first);
212 iter->second.serialize(os);
213
214 ++iter;
215 ++count;
216 }
217 assert(count == pTable.size());
218}
219
220void
221PageTable::unserialize(Checkpoint *cp, const std::string &section)
222{
223 int i = 0, count;
224 paramIn(cp, section, "ptable.size", count);
220 Addr vaddr;
221 TheISA::TlbEntry *entry;
222
223 pTable.clear();
224
225
226 pTable.clear();
227
225 while(i < count) {
226 paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
228 while (i < count) {
229#if !FULL_SYSTEM
230 TheISA::TlbEntry *entry;
231 Addr vaddr;
232
233 paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
227 entry = new TheISA::TlbEntry();
234 entry = new TheISA::TlbEntry();
228 entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
235 entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
229 pTable[vaddr] = *entry;
230 ++i;
236 pTable[vaddr] = *entry;
237 ++i;
238#endif
231 }
232}
233
239 }
240}
241