page_table.cc (6658:f4de76601762) page_table.cc (6818:5a0e3a283826)
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 208 unchanged lines hidden (view full) ---

217 pTable.clear();
218
219 while(i < count) {
220 paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
221 entry = new TheISA::TlbEntry();
222 entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
223 pTable[vaddr] = *entry;
224 ++i;
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 208 unchanged lines hidden (view full) ---

217 pTable.clear();
218
219 while(i < count) {
220 paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
221 entry = new TheISA::TlbEntry();
222 entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
223 pTable[vaddr] = *entry;
224 ++i;
225 }
225 }
226
227 process->M5_pid = pTable[vaddr].asn;
228
229#if THE_ISA == ALPHA_ISA
230 // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work
231 // correctly
232 int id = process->contextIds[0];
233 ThreadContext *tc = process->system->getThreadContext(id);
234 tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57);
235#endif
226}
227
236}
237