page_table.cc (5183:b4decf133fe4) page_table.cc (5184:8782de2949e5)
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
46#include "sim/process.hh"
46#include "sim/sim_object.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
47#include "sim/sim_object.hh"
48#include "sim/system.hh"
49
50using namespace std;
51using namespace TheISA;
52
52PageTable::PageTable(System *_system, Addr _pageSize)
53PageTable::PageTable(Process *_process, Addr _pageSize)
53 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54 system(_system)
55 process(_process)
55{
56 assert(isPowerOf2(pageSize));
57 pTableCache[0].vaddr = 0;
58 pTableCache[1].vaddr = 0;
59 pTableCache[2].vaddr = 0;
60}
61
62PageTable::~PageTable()

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75 PTableItr iter = pTable.find(vaddr);
76
77 if (iter != pTable.end()) {
78 // already mapped
79 fatal("PageTable::allocate: address 0x%x already mapped",
80 vaddr);
81 }
82
56{
57 assert(isPowerOf2(pageSize));
58 pTableCache[0].vaddr = 0;
59 pTableCache[1].vaddr = 0;
60 pTableCache[2].vaddr = 0;
61}
62
63PageTable::~PageTable()

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76 PTableItr iter = pTable.find(vaddr);
77
78 if (iter != pTable.end()) {
79 // already mapped
80 fatal("PageTable::allocate: address 0x%x already mapped",
81 vaddr);
82 }
83
83 pTable[vaddr] = TheISA::TlbEntry(system->new_page());
84 pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
85 process->system->new_page());
84 updateCache(vaddr, pTable[vaddr]);
85 }
86}
87
88bool
89PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
90{
91 Addr page_addr = pageAlign(vaddr);

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117bool
118PageTable::translate(Addr vaddr, Addr &paddr)
119{
120 TheISA::TlbEntry entry;
121 if (!lookup(vaddr, entry)) {
122 DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
123 return false;
124 }
86 updateCache(vaddr, pTable[vaddr]);
87 }
88}
89
90bool
91PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
92{
93 Addr page_addr = pageAlign(vaddr);

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119bool
120PageTable::translate(Addr vaddr, Addr &paddr)
121{
122 TheISA::TlbEntry entry;
123 if (!lookup(vaddr, entry)) {
124 DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
125 return false;
126 }
125 paddr = pageOffset(vaddr) + entry.pageStart;
127 paddr = pageOffset(vaddr) + entry.pageStart();
126 DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
127 return true;
128}
129
130Fault
131PageTable::translate(RequestPtr req)
132{
133 Addr paddr;

--- 53 unchanged lines hidden --- 		128 DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
129 return true;
130}
131
132Fault
133PageTable::translate(RequestPtr req)
134{
135 Addr paddr;

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