page_table.cc (10556:1e3b3c7a0cba) | page_table.cc (10558:426665ec11a9) |
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1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2003 The Regents of The University of Michigan 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 48 unchanged lines hidden (view full) --- 57{ 58} 59 60FuncPageTable::~FuncPageTable() 61{ 62} 63 64void | 1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2003 The Regents of The University of Michigan 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 48 unchanged lines hidden (view full) --- 57{ 58} 59 60FuncPageTable::~FuncPageTable() 61{ 62} 63 64void |
65FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber) | 65FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags) |
66{ | 66{ |
67 bool clobber = flags & Clobber; |
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67 // starting address must be page aligned 68 assert(pageOffset(vaddr) == 0); 69 70 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 71 72 for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { 73 if (!clobber && (pTable.find(vaddr) != pTable.end())) { 74 // already mapped 75 fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr); 76 } 77 | 68 // starting address must be page aligned 69 assert(pageOffset(vaddr) == 0); 70 71 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 72 73 for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { 74 if (!clobber && (pTable.find(vaddr) != pTable.end())) { 75 // already mapped 76 fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr); 77 } 78 |
78 pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr); | 79 pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr, 80 flags & Uncacheable, 81 flags & ReadOnly); |
79 eraseCacheEntry(vaddr); 80 updateCache(vaddr, pTable[vaddr]); 81 } 82} 83 84void 85FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 86{ --- 150 unchanged lines hidden --- | 82 eraseCacheEntry(vaddr); 83 updateCache(vaddr, pTable[vaddr]); 84 } 85} 86 87void 88FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 89{ --- 150 unchanged lines hidden --- |