1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2003 The Regents of The University of Michigan 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 * Ron Dreslinski 31 * Ali Saidi 32 */ 33 34/** 35 * @file 36 * Definitions of functional page table. 37 */ 38#include "mem/page_table.hh" 39 40#include <string> 41 42#include "base/trace.hh"
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43#include "config/the_isa.hh"
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43#include "debug/MMU.hh" 44#include "sim/faults.hh" 45#include "sim/serialize.hh" 46 47using namespace std;
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49using namespace TheISA;
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48
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51EmulationPageTable::~EmulationPageTable()
52{
53 for (auto &iter : pTable)
54 delete iter.second;
55}
56
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49void 50EmulationPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags) 51{ 52 bool clobber = flags & Clobber; 53 // starting address must be page aligned 54 assert(pageOffset(vaddr) == 0); 55 56 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr + size); 57 58 while (size > 0) { 59 auto it = pTable.find(vaddr); 60 if (it != pTable.end()) {
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69 if (clobber) {
70 delete it->second;
71 } else {
72 // already mapped
73 panic("EmulationPageTable::allocate: addr %#x already mapped",
74 vaddr);
75 }
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61 // already mapped 62 panic_if(!clobber, 63 "EmulationPageTable::allocate: addr %#x already mapped", 64 vaddr); 65 it->second = Entry(paddr, flags); |
66 } else {
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77 it = pTable.emplace(vaddr, nullptr).first;
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67 pTable.emplace(vaddr, Entry(paddr, flags)); |
68 } 69
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80 it->second = new TheISA::TlbEntry(pid, vaddr, paddr,
81 flags & Uncacheable,
82 flags & ReadOnly);
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70 size -= pageSize; 71 vaddr += pageSize; 72 paddr += pageSize; 73 } 74} 75 76void 77EmulationPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 78{ 79 assert(pageOffset(vaddr) == 0); 80 assert(pageOffset(new_vaddr) == 0); 81 82 DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr, 83 new_vaddr, size); 84 85 while (size > 0) { 86 auto new_it = pTable.find(new_vaddr); 87 auto old_it = pTable.find(vaddr); 88 assert(old_it != pTable.end() && new_it == pTable.end()); 89 90 new_it->second = old_it->second; 91 pTable.erase(old_it);
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105 new_it->second->updateVaddr(new_vaddr);
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92 size -= pageSize; 93 vaddr += pageSize; 94 new_vaddr += pageSize; 95 } 96} 97 98void 99EmulationPageTable::getMappings(std::vector<std::pair<Addr, Addr>> *addr_maps) 100{ 101 for (auto &iter : pTable)
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116 addr_maps->push_back(make_pair(iter.first, iter.second->pageStart()));
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102 addr_maps->push_back(make_pair(iter.first, iter.second.paddr)); |
103} 104 105void 106EmulationPageTable::unmap(Addr vaddr, int64_t size) 107{ 108 assert(pageOffset(vaddr) == 0); 109
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124 DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
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110 DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr + size); |
111 112 while (size > 0) { 113 auto it = pTable.find(vaddr); 114 assert(it != pTable.end());
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129 delete it->second;
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115 pTable.erase(it); 116 size -= pageSize; 117 vaddr += pageSize; 118 } 119} 120 121bool 122EmulationPageTable::isUnmapped(Addr vaddr, int64_t size) 123{ 124 // starting address must be page aligned 125 assert(pageOffset(vaddr) == 0); 126 127 for (int64_t offset = 0; offset < size; offset += pageSize) 128 if (pTable.find(vaddr + offset) != pTable.end()) 129 return false; 130 131 return true; 132} 133
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149TheISA::TlbEntry *
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134const EmulationPageTable::Entry * |
135EmulationPageTable::lookup(Addr vaddr) 136{ 137 Addr page_addr = pageAlign(vaddr); 138 PTableItr iter = pTable.find(page_addr); 139 if (iter == pTable.end()) 140 return nullptr;
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156 return iter->second;
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141 return &(iter->second); |
142} 143 144bool 145EmulationPageTable::translate(Addr vaddr, Addr &paddr) 146{
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162 TheISA::TlbEntry *entry = lookup(vaddr);
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147 const Entry *entry = lookup(vaddr); |
148 if (!entry) { 149 DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr); 150 return false; 151 }
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167 paddr = pageOffset(vaddr) + entry->pageStart();
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152 paddr = pageOffset(vaddr) + entry->paddr; |
153 DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr); 154 return true; 155} 156 157Fault 158EmulationPageTable::translate(RequestPtr req) 159{ 160 Addr paddr; 161 assert(pageAlign(req->getVaddr() + req->getSize() - 1) == 162 pageAlign(req->getVaddr())); 163 if (!translate(req->getVaddr(), paddr)) 164 return Fault(new GenericPageTableFault(req->getVaddr())); 165 req->setPaddr(paddr); 166 if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) { 167 panic("Request spans page boundaries!\n"); 168 return NoFault; 169 } 170 return NoFault; 171} 172 173void 174EmulationPageTable::serialize(CheckpointOut &cp) const 175{ 176 paramOut(cp, "ptable.size", pTable.size()); 177 178 PTable::size_type count = 0; 179 for (auto &pte : pTable) { 180 ScopedCheckpointSection sec(cp, csprintf("Entry%d", count++)); 181 182 paramOut(cp, "vaddr", pte.first);
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198 pte.second->serialize(cp);
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183 paramOut(cp, "paddr", pte.second.paddr); 184 paramOut(cp, "flags", pte.second.flags); |
185 } 186 assert(count == pTable.size()); 187} 188 189void 190EmulationPageTable::unserialize(CheckpointIn &cp) 191{ 192 int count; 193 paramIn(cp, "ptable.size", count); 194 195 for (int i = 0; i < count; ++i) { 196 ScopedCheckpointSection sec(cp, csprintf("Entry%d", i)); 197
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212 TheISA::TlbEntry *entry = new TheISA::TlbEntry();
213 entry->unserialize(cp);
214
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198 Addr vaddr;
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216 paramIn(cp, "vaddr", vaddr);
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199 UNSERIALIZE_SCALAR(vaddr); 200 Addr paddr; 201 uint64_t flags; 202 UNSERIALIZE_SCALAR(paddr); 203 UNSERIALIZE_SCALAR(flags); |
204
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218 pTable[vaddr] = entry;
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205 pTable.emplace(vaddr, Entry(paddr, flags)); |
206 } 207} 208
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