1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40 41#include "base/bitfield.hh" 42#include "base/intmath.hh" 43#include "base/trace.hh" 44#include "config/the_isa.hh" 45#include "debug/MMU.hh" 46#include "mem/page_table.hh" 47#include "sim/faults.hh" |
48#include "sim/sim_object.hh" |
49 50using namespace std; 51using namespace TheISA; 52 |
53PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize) |
54 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), |
55 pid(_pid), _name(__name) |
56{ 57 assert(isPowerOf2(pageSize)); 58 pTableCache[0].vaddr = 0; 59 pTableCache[1].vaddr = 0; 60 pTableCache[2].vaddr = 0; 61} 62 63PageTable::~PageTable() 64{ 65} 66 67void |
68PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber) |
69{ 70 // starting address must be page aligned 71 assert(pageOffset(vaddr) == 0); 72 73 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 74 |
75 for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { 76 if (!clobber && (pTable.find(vaddr) != pTable.end())) { |
77 // already mapped |
78 fatal("PageTable::allocate: address 0x%x already mapped", vaddr); |
79 } 80 |
81 pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr); |
82 updateCache(vaddr, pTable[vaddr]); 83 } 84} 85 86void 87PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 88{ 89 assert(pageOffset(vaddr) == 0); --- 10 unchanged lines hidden (view full) --- 100 pTable[new_vaddr] = pTable[vaddr]; 101 pTable.erase(vaddr); 102 pTable[new_vaddr].updateVaddr(new_vaddr); 103 updateCache(new_vaddr, pTable[new_vaddr]); 104 } 105} 106 107void |
108PageTable::unmap(Addr vaddr, int64_t size) |
109{ 110 assert(pageOffset(vaddr) == 0); 111 |
112 DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size); |
113 114 for (; size > 0; size -= pageSize, vaddr += pageSize) { 115 PTableItr iter = pTable.find(vaddr); 116 117 assert(iter != pTable.end()); 118 119 pTable.erase(vaddr); 120 } 121 122} 123 124bool |
125PageTable::isUnmapped(Addr vaddr, int64_t size) 126{ 127 // starting address must be page aligned 128 assert(pageOffset(vaddr) == 0); 129 130 for (; size > 0; size -= pageSize, vaddr += pageSize) { 131 if (pTable.find(vaddr) != pTable.end()) { 132 return false; 133 } 134 } 135 136 return true; 137} 138 139bool |
140PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) 141{ 142 Addr page_addr = pageAlign(vaddr); 143 144 if (pTableCache[0].vaddr == page_addr) { 145 entry = pTableCache[0].entry; 146 return true; 147 } --- 52 unchanged lines hidden (view full) --- 200{ 201 paramOut(os, "ptable.size", pTable.size()); 202 203 PTable::size_type count = 0; 204 205 PTableItr iter = pTable.begin(); 206 PTableItr end = pTable.end(); 207 while (iter != end) { |
208 os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n"; |
209 210 paramOut(os, "vaddr", iter->first); 211 iter->second.serialize(os); 212 213 ++iter; 214 ++count; 215 } 216 assert(count == pTable.size()); --- 6 unchanged lines hidden (view full) --- 223 paramIn(cp, section, "ptable.size", count); 224 225 pTable.clear(); 226 227 while (i < count) { 228 TheISA::TlbEntry *entry; 229 Addr vaddr; 230 |
231 paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); |
232 entry = new TheISA::TlbEntry(); |
233 entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); |
234 pTable[vaddr] = *entry; 235 ++i; 236 } 237} 238 |