1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Ron Dreslinski 30 * Ali Saidi 31 */ 32 33/** 34 * @file 35 * Definitions of page table. 36 */ 37#include <fstream> 38#include <map> 39#include <string> 40 41#include "base/bitfield.hh" 42#include "base/intmath.hh" 43#include "base/trace.hh" 44#include "config/the_isa.hh" 45#include "debug/MMU.hh" 46#include "mem/page_table.hh" 47#include "sim/faults.hh"
| 1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Ron Dreslinski 30 * Ali Saidi 31 */ 32 33/** 34 * @file 35 * Definitions of page table. 36 */ 37#include <fstream> 38#include <map> 39#include <string> 40 41#include "base/bitfield.hh" 42#include "base/intmath.hh" 43#include "base/trace.hh" 44#include "config/the_isa.hh" 45#include "debug/MMU.hh" 46#include "mem/page_table.hh" 47#include "sim/faults.hh"
|
48#include "sim/process.hh"
| |
49#include "sim/sim_object.hh"
| 48#include "sim/sim_object.hh"
|
50#include "sim/system.hh"
| |
51 52using namespace std; 53using namespace TheISA; 54
| 49 50using namespace std; 51using namespace TheISA; 52
|
55PageTable::PageTable(Process *_process, Addr _pageSize)
| 53PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize)
|
56 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
| 54 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
|
57 process(_process)
| 55 pid(_pid), _name(__name)
|
58{ 59 assert(isPowerOf2(pageSize)); 60 pTableCache[0].vaddr = 0; 61 pTableCache[1].vaddr = 0; 62 pTableCache[2].vaddr = 0; 63} 64 65PageTable::~PageTable() 66{ 67} 68 69void
| 56{ 57 assert(isPowerOf2(pageSize)); 58 pTableCache[0].vaddr = 0; 59 pTableCache[1].vaddr = 0; 60 pTableCache[2].vaddr = 0; 61} 62 63PageTable::~PageTable() 64{ 65} 66 67void
|
70PageTable::allocate(Addr vaddr, int64_t size)
| 68PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
|
71{ 72 // starting address must be page aligned 73 assert(pageOffset(vaddr) == 0); 74 75 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 76
| 69{ 70 // starting address must be page aligned 71 assert(pageOffset(vaddr) == 0); 72 73 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 74
|
77 for (; size > 0; size -= pageSize, vaddr += pageSize) { 78 PTableItr iter = pTable.find(vaddr); 79 80 if (iter != pTable.end()) {
| 75 for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { 76 if (!clobber && (pTable.find(vaddr) != pTable.end())) {
|
81 // already mapped
| 77 // already mapped
|
82 fatal("PageTable::allocate: address 0x%x already mapped", 83 vaddr);
| 78 fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
|
84 } 85
| 79 } 80
|
86 pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr, 87 process->system->new_page());
| 81 pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
|
88 updateCache(vaddr, pTable[vaddr]); 89 } 90} 91 92void 93PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 94{ 95 assert(pageOffset(vaddr) == 0); 96 assert(pageOffset(new_vaddr) == 0); 97 98 DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr, 99 new_vaddr, size); 100 101 for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) { 102 PTableItr iter = pTable.find(vaddr); 103 104 assert(iter != pTable.end()); 105 106 pTable[new_vaddr] = pTable[vaddr]; 107 pTable.erase(vaddr); 108 pTable[new_vaddr].updateVaddr(new_vaddr); 109 updateCache(new_vaddr, pTable[new_vaddr]); 110 } 111} 112 113void
| 82 updateCache(vaddr, pTable[vaddr]); 83 } 84} 85 86void 87PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) 88{ 89 assert(pageOffset(vaddr) == 0); 90 assert(pageOffset(new_vaddr) == 0); 91 92 DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr, 93 new_vaddr, size); 94 95 for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) { 96 PTableItr iter = pTable.find(vaddr); 97 98 assert(iter != pTable.end()); 99 100 pTable[new_vaddr] = pTable[vaddr]; 101 pTable.erase(vaddr); 102 pTable[new_vaddr].updateVaddr(new_vaddr); 103 updateCache(new_vaddr, pTable[new_vaddr]); 104 } 105} 106 107void
|
114PageTable::deallocate(Addr vaddr, int64_t size)
| 108PageTable::unmap(Addr vaddr, int64_t size)
|
115{ 116 assert(pageOffset(vaddr) == 0); 117
| 109{ 110 assert(pageOffset(vaddr) == 0); 111
|
118 DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size);
| 112 DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
|
119 120 for (; size > 0; size -= pageSize, vaddr += pageSize) { 121 PTableItr iter = pTable.find(vaddr); 122 123 assert(iter != pTable.end()); 124 125 pTable.erase(vaddr); 126 } 127 128} 129 130bool
| 113 114 for (; size > 0; size -= pageSize, vaddr += pageSize) { 115 PTableItr iter = pTable.find(vaddr); 116 117 assert(iter != pTable.end()); 118 119 pTable.erase(vaddr); 120 } 121 122} 123 124bool
|
| 125PageTable::isUnmapped(Addr vaddr, int64_t size) 126{ 127 // starting address must be page aligned 128 assert(pageOffset(vaddr) == 0); 129 130 for (; size > 0; size -= pageSize, vaddr += pageSize) { 131 if (pTable.find(vaddr) != pTable.end()) { 132 return false; 133 } 134 } 135 136 return true; 137} 138 139bool
|
131PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) 132{ 133 Addr page_addr = pageAlign(vaddr); 134 135 if (pTableCache[0].vaddr == page_addr) { 136 entry = pTableCache[0].entry; 137 return true; 138 } 139 if (pTableCache[1].vaddr == page_addr) { 140 entry = pTableCache[1].entry; 141 return true; 142 } 143 if (pTableCache[2].vaddr == page_addr) { 144 entry = pTableCache[2].entry; 145 return true; 146 } 147 148 PTableItr iter = pTable.find(page_addr); 149 150 if (iter == pTable.end()) { 151 return false; 152 } 153 154 updateCache(page_addr, iter->second); 155 entry = iter->second; 156 return true; 157} 158 159bool 160PageTable::translate(Addr vaddr, Addr &paddr) 161{ 162 TheISA::TlbEntry entry; 163 if (!lookup(vaddr, entry)) { 164 DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr); 165 return false; 166 } 167 paddr = pageOffset(vaddr) + entry.pageStart(); 168 DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr); 169 return true; 170} 171 172Fault 173PageTable::translate(RequestPtr req) 174{ 175 Addr paddr; 176 assert(pageAlign(req->getVaddr() + req->getSize() - 1) 177 == pageAlign(req->getVaddr())); 178 if (!translate(req->getVaddr(), paddr)) { 179 return Fault(new GenericPageTableFault(req->getVaddr())); 180 } 181 req->setPaddr(paddr); 182 if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) { 183 panic("Request spans page boundaries!\n"); 184 return NoFault; 185 } 186 return NoFault; 187} 188 189void 190PageTable::serialize(std::ostream &os) 191{ 192 paramOut(os, "ptable.size", pTable.size()); 193 194 PTable::size_type count = 0; 195 196 PTableItr iter = pTable.begin(); 197 PTableItr end = pTable.end(); 198 while (iter != end) {
| 140PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) 141{ 142 Addr page_addr = pageAlign(vaddr); 143 144 if (pTableCache[0].vaddr == page_addr) { 145 entry = pTableCache[0].entry; 146 return true; 147 } 148 if (pTableCache[1].vaddr == page_addr) { 149 entry = pTableCache[1].entry; 150 return true; 151 } 152 if (pTableCache[2].vaddr == page_addr) { 153 entry = pTableCache[2].entry; 154 return true; 155 } 156 157 PTableItr iter = pTable.find(page_addr); 158 159 if (iter == pTable.end()) { 160 return false; 161 } 162 163 updateCache(page_addr, iter->second); 164 entry = iter->second; 165 return true; 166} 167 168bool 169PageTable::translate(Addr vaddr, Addr &paddr) 170{ 171 TheISA::TlbEntry entry; 172 if (!lookup(vaddr, entry)) { 173 DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr); 174 return false; 175 } 176 paddr = pageOffset(vaddr) + entry.pageStart(); 177 DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr); 178 return true; 179} 180 181Fault 182PageTable::translate(RequestPtr req) 183{ 184 Addr paddr; 185 assert(pageAlign(req->getVaddr() + req->getSize() - 1) 186 == pageAlign(req->getVaddr())); 187 if (!translate(req->getVaddr(), paddr)) { 188 return Fault(new GenericPageTableFault(req->getVaddr())); 189 } 190 req->setPaddr(paddr); 191 if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) { 192 panic("Request spans page boundaries!\n"); 193 return NoFault; 194 } 195 return NoFault; 196} 197 198void 199PageTable::serialize(std::ostream &os) 200{ 201 paramOut(os, "ptable.size", pTable.size()); 202 203 PTable::size_type count = 0; 204 205 PTableItr iter = pTable.begin(); 206 PTableItr end = pTable.end(); 207 while (iter != end) {
|
199 os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
| 208 os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
|
200 201 paramOut(os, "vaddr", iter->first); 202 iter->second.serialize(os); 203 204 ++iter; 205 ++count; 206 } 207 assert(count == pTable.size()); 208} 209 210void 211PageTable::unserialize(Checkpoint *cp, const std::string §ion) 212{ 213 int i = 0, count; 214 paramIn(cp, section, "ptable.size", count); 215 216 pTable.clear(); 217 218 while (i < count) { 219 TheISA::TlbEntry *entry; 220 Addr vaddr; 221
| 209 210 paramOut(os, "vaddr", iter->first); 211 iter->second.serialize(os); 212 213 ++iter; 214 ++count; 215 } 216 assert(count == pTable.size()); 217} 218 219void 220PageTable::unserialize(Checkpoint *cp, const std::string §ion) 221{ 222 int i = 0, count; 223 paramIn(cp, section, "ptable.size", count); 224 225 pTable.clear(); 226 227 while (i < count) { 228 TheISA::TlbEntry *entry; 229 Addr vaddr; 230
|
222 paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
| 231 paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
|
223 entry = new TheISA::TlbEntry();
| 232 entry = new TheISA::TlbEntry();
|
224 entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
| 233 entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
|
225 pTable[vaddr] = *entry; 226 ++i; 227 } 228} 229
| 234 pTable[vaddr] = *entry; 235 ++i; 236 } 237} 238
|