1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Ron Dreslinski
| 1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Ron Dreslinski
|
| 30 * Ali Saidi
|
30 */
31
32/**
33 * @file
34 * Definitions of page table.
35 */
36#include <string>
37#include <map>
38#include <fstream>
39
40#include "arch/faults.hh"
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "mem/page_table.hh"
45#include "sim/builder.hh"
46#include "sim/sim_object.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
52PageTable::PageTable(System *_system, Addr _pageSize)
53 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54 system(_system)
55{
56 assert(isPowerOf2(pageSize));
57 pTableCache[0].vaddr = 0;
58 pTableCache[1].vaddr = 0;
59 pTableCache[2].vaddr = 0;
60}
61
62PageTable::~PageTable()
63{
64}
65
66Fault
67PageTable::page_check(Addr addr, int64_t size) const
68{
69 if (size < sizeof(uint64_t)) {
70 if (!isPowerOf2(size)) {
71 panic("Invalid request size!\n");
72 return genMachineCheckFault();
73 }
74
75 if ((size - 1) & addr)
76 return genAlignmentFault();
77 }
78 else {
79 if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
80 panic("Invalid request size!\n");
81 return genMachineCheckFault();
82 }
83
84 if ((sizeof(uint64_t) - 1) & addr)
85 return genAlignmentFault();
86 }
87
88 return NoFault;
89}
90
91
92
93
94void
95PageTable::allocate(Addr vaddr, int64_t size)
96{
97 // starting address must be page aligned
98 assert(pageOffset(vaddr) == 0);
99
| 31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <string>
38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
46#include "sim/builder.hh"
47#include "sim/sim_object.hh"
48#include "sim/system.hh"
49
50using namespace std;
51using namespace TheISA;
52
53PageTable::PageTable(System *_system, Addr _pageSize)
54 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
55 system(_system)
56{
57 assert(isPowerOf2(pageSize));
58 pTableCache[0].vaddr = 0;
59 pTableCache[1].vaddr = 0;
60 pTableCache[2].vaddr = 0;
61}
62
63PageTable::~PageTable()
64{
65}
66
67Fault
68PageTable::page_check(Addr addr, int64_t size) const
69{
70 if (size < sizeof(uint64_t)) {
71 if (!isPowerOf2(size)) {
72 panic("Invalid request size!\n");
73 return genMachineCheckFault();
74 }
75
76 if ((size - 1) & addr)
77 return genAlignmentFault();
78 }
79 else {
80 if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
81 panic("Invalid request size!\n");
82 return genMachineCheckFault();
83 }
84
85 if ((sizeof(uint64_t) - 1) & addr)
86 return genAlignmentFault();
87 }
88
89 return NoFault;
90}
91
92
93
94
95void
96PageTable::allocate(Addr vaddr, int64_t size)
97{
98 // starting address must be page aligned
99 assert(pageOffset(vaddr) == 0);
100
|
| 101 DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
102
|
100 for (; size > 0; size -= pageSize, vaddr += pageSize) {
101 m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
102
103 if (iter != pTable.end()) {
104 // already mapped
105 fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
106 }
107
108 pTable[vaddr] = system->new_page();
109 pTableCache[2].paddr = pTableCache[1].paddr;
110 pTableCache[2].vaddr = pTableCache[1].vaddr;
111 pTableCache[1].paddr = pTableCache[0].paddr;
112 pTableCache[1].vaddr = pTableCache[0].vaddr;
113 pTableCache[0].paddr = pTable[vaddr];
114 pTableCache[0].vaddr = vaddr;
115 }
116}
117
118
119
120bool
121PageTable::translate(Addr vaddr, Addr &paddr)
122{
123 Addr page_addr = pageAlign(vaddr);
124 paddr = 0;
125
126 if (pTableCache[0].vaddr == vaddr) {
127 paddr = pTableCache[0].paddr;
128 return true;
129 }
130 if (pTableCache[1].vaddr == vaddr) {
131 paddr = pTableCache[1].paddr;
132 return true;
133 }
134 if (pTableCache[2].vaddr == vaddr) {
135 paddr = pTableCache[2].paddr;
136 return true;
137 }
138
139 m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
140
141 if (iter == pTable.end()) {
142 return false;
143 }
144
145 paddr = iter->second + pageOffset(vaddr);
146 return true;
147}
148
149
150Fault
151PageTable::translate(RequestPtr &req)
152{
153 Addr paddr;
154 assert(pageAlign(req->getVaddr() + req->getSize() - 1)
155 == pageAlign(req->getVaddr()));
156 if (!translate(req->getVaddr(), paddr)) {
157 return genPageTableFault(req->getVaddr());
158 }
159 req->setPaddr(paddr);
160 return page_check(req->getPaddr(), req->getSize());
161}
| 103 for (; size > 0; size -= pageSize, vaddr += pageSize) {
104 m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
105
106 if (iter != pTable.end()) {
107 // already mapped
108 fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
109 }
110
111 pTable[vaddr] = system->new_page();
112 pTableCache[2].paddr = pTableCache[1].paddr;
113 pTableCache[2].vaddr = pTableCache[1].vaddr;
114 pTableCache[1].paddr = pTableCache[0].paddr;
115 pTableCache[1].vaddr = pTableCache[0].vaddr;
116 pTableCache[0].paddr = pTable[vaddr];
117 pTableCache[0].vaddr = vaddr;
118 }
119}
120
121
122
123bool
124PageTable::translate(Addr vaddr, Addr &paddr)
125{
126 Addr page_addr = pageAlign(vaddr);
127 paddr = 0;
128
129 if (pTableCache[0].vaddr == vaddr) {
130 paddr = pTableCache[0].paddr;
131 return true;
132 }
133 if (pTableCache[1].vaddr == vaddr) {
134 paddr = pTableCache[1].paddr;
135 return true;
136 }
137 if (pTableCache[2].vaddr == vaddr) {
138 paddr = pTableCache[2].paddr;
139 return true;
140 }
141
142 m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
143
144 if (iter == pTable.end()) {
145 return false;
146 }
147
148 paddr = iter->second + pageOffset(vaddr);
149 return true;
150}
151
152
153Fault
154PageTable::translate(RequestPtr &req)
155{
156 Addr paddr;
157 assert(pageAlign(req->getVaddr() + req->getSize() - 1)
158 == pageAlign(req->getVaddr()));
159 if (!translate(req->getVaddr(), paddr)) {
160 return genPageTableFault(req->getVaddr());
161 }
162 req->setPaddr(paddr);
163 return page_check(req->getPaddr(), req->getSize());
164}
|
| 165
166void
167PageTable::serialize(std::ostream &os)
168{
169 paramOut(os, "ptable.size", pTable.size());
170 int count = 0;
171
172 m5::hash_map<Addr,Addr>::iterator iter;
173 while (iter != pTable.end()) {
174 paramOut(os, csprintf("ptable.entry%dvaddr", count),iter->first);
175 paramOut(os, csprintf("ptable.entry%dpaddr", count),iter->second);
176 ++count;
177 }
178 assert(count == pTable.size());
179}
180
181void
182PageTable::unserialize(Checkpoint *cp, const std::string §ion)
183{
184 int i = 0, count;
185 paramIn(cp, section, "ptable.size", count);
186 Addr vaddr, paddr;
187
188 pTable.clear();
189
190 while(i < count) {
191 paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr);
192 paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr);
193 pTable[vaddr] = paddr;
194 ++i;
195 }
196
197}
198
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