1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Ron Dreslinski
30 */
31
32/**
33 * @file
34 * Definitions of page table.
35 */
36#include <string>
37#include <map>
38#include <fstream>
39
40#include "arch/faults.hh"
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "mem/page_table.hh"
45#include "sim/builder.hh"
46#include "sim/sim_object.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
52PageTable::PageTable(System *_system, Addr _pageSize)
53 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54 system(_system)
55{
56 assert(isPowerOf2(pageSize));
| 1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Ron Dreslinski
30 */
31
32/**
33 * @file
34 * Definitions of page table.
35 */
36#include <string>
37#include <map>
38#include <fstream>
39
40#include "arch/faults.hh"
41#include "base/bitfield.hh"
42#include "base/intmath.hh"
43#include "base/trace.hh"
44#include "mem/page_table.hh"
45#include "sim/builder.hh"
46#include "sim/sim_object.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
52PageTable::PageTable(System *_system, Addr _pageSize)
53 : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54 system(_system)
55{
56 assert(isPowerOf2(pageSize));
|
| 57 pTableCache[0].vaddr = 0;
58 pTableCache[1].vaddr = 0;
59 pTableCache[2].vaddr = 0;
|
57}
58
59PageTable::~PageTable()
60{
61}
62
63Fault
64PageTable::page_check(Addr addr, int size) const
65{
66 if (size < sizeof(uint64_t)) {
67 if (!isPowerOf2(size)) {
68 panic("Invalid request size!\n");
69 return genMachineCheckFault();
70 }
71
72 if ((size - 1) & addr)
73 return genAlignmentFault();
74 }
75 else {
76 if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
77 panic("Invalid request size!\n");
78 return genMachineCheckFault();
79 }
80
81 if ((sizeof(uint64_t) - 1) & addr)
82 return genAlignmentFault();
83 }
84
85 return NoFault;
86}
87
88
89
90
91void
92PageTable::allocate(Addr vaddr, int size)
93{
94 // starting address must be page aligned
95 assert(pageOffset(vaddr) == 0);
96
97 for (; size > 0; size -= pageSize, vaddr += pageSize) {
| 60}
61
62PageTable::~PageTable()
63{
64}
65
66Fault
67PageTable::page_check(Addr addr, int size) const
68{
69 if (size < sizeof(uint64_t)) {
70 if (!isPowerOf2(size)) {
71 panic("Invalid request size!\n");
72 return genMachineCheckFault();
73 }
74
75 if ((size - 1) & addr)
76 return genAlignmentFault();
77 }
78 else {
79 if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
80 panic("Invalid request size!\n");
81 return genMachineCheckFault();
82 }
83
84 if ((sizeof(uint64_t) - 1) & addr)
85 return genAlignmentFault();
86 }
87
88 return NoFault;
89}
90
91
92
93
94void
95PageTable::allocate(Addr vaddr, int size)
96{
97 // starting address must be page aligned
98 assert(pageOffset(vaddr) == 0);
99
100 for (; size > 0; size -= pageSize, vaddr += pageSize) {
|
98 std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
| 101 m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
|
99
100 if (iter != pTable.end()) {
101 // already mapped
102 fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
103 }
104
105 pTable[vaddr] = system->new_page();
| 102
103 if (iter != pTable.end()) {
104 // already mapped
105 fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
106 }
107
108 pTable[vaddr] = system->new_page();
|
| 109 pTableCache[2].paddr = pTableCache[1].paddr;
110 pTableCache[2].vaddr = pTableCache[1].vaddr;
111 pTableCache[1].paddr = pTableCache[0].paddr;
112 pTableCache[1].vaddr = pTableCache[0].vaddr;
113 pTableCache[0].paddr = pTable[vaddr];
114 pTableCache[0].vaddr = vaddr;
|
106 }
107}
108
109
110
111bool
112PageTable::translate(Addr vaddr, Addr &paddr)
113{
114 Addr page_addr = pageAlign(vaddr);
| 115 }
116}
117
118
119
120bool
121PageTable::translate(Addr vaddr, Addr &paddr)
122{
123 Addr page_addr = pageAlign(vaddr);
|
115 std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
| 124 paddr = 0;
|
116
| 125
|
| 126 if (pTableCache[0].vaddr == vaddr) {
127 paddr = pTableCache[0].paddr;
128 return true;
129 }
130 if (pTableCache[1].vaddr == vaddr) {
131 paddr = pTableCache[1].paddr;
132 return true;
133 }
134 if (pTableCache[2].vaddr == vaddr) {
135 paddr = pTableCache[2].paddr;
136 return true;
137 }
138
139 m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
140
|
117 if (iter == pTable.end()) {
118 return false;
119 }
120
121 paddr = iter->second + pageOffset(vaddr);
122 return true;
123}
124
125
126Fault
127PageTable::translate(RequestPtr &req)
128{
129 Addr paddr;
130 assert(pageAlign(req->getVaddr() + req->getSize() - 1)
131 == pageAlign(req->getVaddr()));
132 if (!translate(req->getVaddr(), paddr)) {
133 return genPageTableFault(req->getVaddr());
134 }
135 req->setPaddr(paddr);
136 return page_check(req->getPaddr(), req->getSize());
137}
| 141 if (iter == pTable.end()) {
142 return false;
143 }
144
145 paddr = iter->second + pageOffset(vaddr);
146 return true;
147}
148
149
150Fault
151PageTable::translate(RequestPtr &req)
152{
153 Addr paddr;
154 assert(pageAlign(req->getVaddr() + req->getSize() - 1)
155 == pageAlign(req->getVaddr()));
156 if (!translate(req->getVaddr(), paddr)) {
157 return genPageTableFault(req->getVaddr());
158 }
159 req->setPaddr(paddr);
160 return page_check(req->getPaddr(), req->getSize());
161}
|