1/* 2 * Copyright (c) 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Andreas Sandberg 43 */ 44 45#include "arch/isa_traits.hh" |
46#include "config/the_isa.hh" 47#include "mem/packet.hh" 48#include "sim/byteswap.hh" 49 50#ifndef __MEM_PACKET_ACCESS_HH__ 51#define __MEM_PACKET_ACCESS_HH__ 52 53template <typename T> 54inline T 55Packet::getRaw() const 56{ 57 assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA)); 58 assert(sizeof(T) <= size); 59 return *(T*)data; 60} 61 62template <typename T> 63inline void 64Packet::setRaw(T v) 65{ 66 assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA)); 67 assert(sizeof(T) <= size); 68 *(T*)data = v; 69} 70 71 72template <typename T> 73inline T 74Packet::getBE() const 75{ 76 return betoh(getRaw<T>()); 77} 78 79template <typename T> 80inline T 81Packet::getLE() const 82{ 83 return letoh(getRaw<T>()); 84} 85 86template <typename T> 87inline T 88Packet::get(ByteOrder endian) const 89{ 90 switch (endian) { 91 case BigEndianByteOrder: 92 return getBE<T>(); 93 94 case LittleEndianByteOrder: 95 return getLE<T>(); 96 97 default: 98 panic("Illegal byte order in Packet::get()\n"); 99 }; 100} 101 102template <typename T> 103inline T 104Packet::get() const 105{ 106 return TheISA::gtoh(getRaw<T>()); 107} 108 109template <typename T> 110inline void 111Packet::setBE(T v) 112{ 113 setRaw(htobe(v)); 114} 115 116template <typename T> 117inline void 118Packet::setLE(T v) 119{ 120 setRaw(htole(v)); 121} 122 123template <typename T> 124inline void 125Packet::set(T v, ByteOrder endian) 126{ 127 switch (endian) { 128 case BigEndianByteOrder: 129 return setBE<T>(v); 130 131 case LittleEndianByteOrder: 132 return setLE<T>(v); 133 134 default: 135 panic("Illegal byte order in Packet::set()\n"); 136 }; 137} 138 139template <typename T> 140inline void 141Packet::set(T v) 142{ 143 setRaw(TheISA::htog(v)); 144} 145 146#endif //__MEM_PACKET_ACCESS_HH__ |