packet.hh (4473:fa451e5f9f06) packet.hh (4489:381fcb5b6c31)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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56
57//Coherence Flags
58#define NACKED_LINE (1 << 0)
59#define SATISFIED (1 << 1)
60#define SHARED_LINE (1 << 2)
61#define CACHE_LINE_FILL (1 << 3)
62#define COMPRESSED (1 << 4)
63#define NO_ALLOCATE (1 << 5)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 47 unchanged lines hidden (view full) ---

56
57//Coherence Flags
58#define NACKED_LINE (1 << 0)
59#define SATISFIED (1 << 1)
60#define SHARED_LINE (1 << 2)
61#define CACHE_LINE_FILL (1 << 3)
62#define COMPRESSED (1 << 4)
63#define NO_ALLOCATE (1 << 5)
64#define SNOOP_COMMIT (1 << 6)
64
65
65#define EXPRESS_SNOOP (1 << 7)
66
67class MemCmd
68{
69 public:
70
71 /** List of all commands associated with a packet. */
72 enum Command
73 {
74 InvalidCmd,
75 ReadReq,
66
67class MemCmd
68{
69 public:
70
71 /** List of all commands associated with a packet. */
72 enum Command
73 {
74 InvalidCmd,
75 ReadReq,
76 ReadResp,
77 WriteReq,
76 WriteReq,
77 WriteReqNoAck,
78 ReadResp,
78 WriteResp,
79 Writeback,
79 WriteResp,
80 Writeback,
80 WritebackAck,
81 SoftPFReq,
82 HardPFReq,
83 SoftPFResp,
84 HardPFResp,
85 InvalidateReq,
86 WriteInvalidateReq,
87 WriteInvalidateResp,
88 UpgradeReq,

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501
502 /** If there isn't data in the packet, allocate some. */
503 void allocate();
504
505 /** Do the packet modify the same addresses. */
506 bool intersect(PacketPtr p);
507};
508
81 SoftPFReq,
82 HardPFReq,
83 SoftPFResp,
84 HardPFResp,
85 InvalidateReq,
86 WriteInvalidateReq,
87 WriteInvalidateResp,
88 UpgradeReq,

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501
502 /** If there isn't data in the packet, allocate some. */
503 void allocate();
504
505 /** Do the packet modify the same addresses. */
506 bool intersect(PacketPtr p);
507};
508
509/** This function given a functional packet and a timing packet either satisfies
510 * the timing packet, or updates the timing packet to reflect the updated state
511 * in the timing packet. It returns if the functional packet should continue to
512 * traverse the memory hierarchy or not.
509/** This function given a functional packet and a timing packet either
510 * satisfies the timing packet, or updates the timing packet to
511 * reflect the updated state in the timing packet. It returns if the
512 * functional packet should continue to traverse the memory hierarchy
513 * or not.
513 */
514bool fixPacket(PacketPtr func, PacketPtr timing);
515
514 */
515bool fixPacket(PacketPtr func, PacketPtr timing);
516
516/** This function is a wrapper for the fixPacket field that toggles the hasData bit
517 * it is used when a response is waiting in the caches, but hasn't been marked as a
518 * response yet (so the fixPacket needs to get the correct value for the hasData)
517/** This function is a wrapper for the fixPacket field that toggles
518 * the hasData bit it is used when a response is waiting in the
519 * caches, but hasn't been marked as a response yet (so the fixPacket
520 * needs to get the correct value for the hasData)
519 */
520bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing);
521
522std::ostream & operator<<(std::ostream &o, const Packet &p);
523
524#endif //__MEM_PACKET_HH
521 */
522bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing);
523
524std::ostream & operator<<(std::ostream &o, const Packet &p);
525
526#endif //__MEM_PACKET_HH