94,101d93
< // WriteInvalidateReq transactions used to be generated by the
< // DMA ports when writing full blocks to memory, however, it
< // is not used anymore since we put the I/O cache in place to
< // deal with partial block writes. Hence, WriteInvalidateReq
< // and WriteInvalidateResp are currently unused. The
< // implication is that the I/O cache does read-exclusive
< // operations on every full-cache-block DMA, and ultimately
< // this needs to be fixed.
< // WriteInvalidateReq transactions used to be generated by the
< // DMA ports when writing full blocks to memory, however, it
< // is not used anymore since we put the I/O cache in place to
< // deal with partial block writes. Hence, WriteInvalidateReq
< // and WriteInvalidateResp are currently unused. The
< // implication is that the I/O cache does read-exclusive
< // operations on every full-cache-block DMA, and ultimately
< // this needs to be fixed.