3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * Copyright (c) 2010 Advanced Micro Devices, Inc. 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Steve Reinhardt 43 */ 44 45/** 46 * @file 47 * Definition of the Packet Class, a packet is a transaction occuring 48 * between a single level of the memory heirarchy (ie L1->L2). 49 */ 50 51#include <cstring> 52#include <iostream> 53 54#include "base/cprintf.hh" 55#include "base/misc.hh" 56#include "base/trace.hh" 57#include "mem/packet.hh" 58 59using namespace std; 60 61// The one downside to bitsets is that static initializers can get ugly. 62#define SET1(a1) (1 << (a1)) 63#define SET2(a1, a2) (SET1(a1) | SET1(a2)) 64#define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3)) 65#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4)) 66#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5)) 67#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6)) 68 69const MemCmd::CommandInfo 70MemCmd::commandInfo[] = 71{ 72 /* InvalidCmd */ 73 { 0, InvalidCmd, "InvalidCmd" }, 74 /* ReadReq */ 75 { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" }, 76 /* ReadResp */ 77 { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" }, 78 /* ReadRespWithInvalidate */ 79 { SET4(IsRead, IsResponse, HasData, IsInvalidate), 80 InvalidCmd, "ReadRespWithInvalidate" }, 81 /* WriteReq */ 82 { SET5(IsWrite, NeedsExclusive, IsRequest, NeedsResponse, HasData), 83 WriteResp, "WriteReq" }, 84 /* WriteResp */ 85 { SET3(IsWrite, NeedsExclusive, IsResponse), InvalidCmd, "WriteResp" }, 86 /* Writeback */ 87 { SET4(IsWrite, NeedsExclusive, IsRequest, HasData), 88 InvalidCmd, "Writeback" }, 89 /* SoftPFReq */ 90 { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), 91 SoftPFResp, "SoftPFReq" }, 92 /* HardPFReq */ 93 { SET4(IsRead, IsRequest, IsHWPrefetch, NeedsResponse), 94 HardPFResp, "HardPFReq" }, 95 /* SoftPFResp */ 96 { SET4(IsRead, IsResponse, IsSWPrefetch, HasData), 97 InvalidCmd, "SoftPFResp" }, 98 /* HardPFResp */ 99 { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), 100 InvalidCmd, "HardPFResp" }, 101 /* WriteInvalidateReq (currently unused, see packet.hh) */ 102 { SET6(IsWrite, NeedsExclusive, IsInvalidate, 103 IsRequest, HasData, NeedsResponse), 104 WriteInvalidateResp, "WriteInvalidateReq" }, 105 /* WriteInvalidateResp (currently unused, see packet.hh) */ 106 { SET3(IsWrite, NeedsExclusive, IsResponse), 107 InvalidCmd, "WriteInvalidateResp" }, 108 /* UpgradeReq */ 109 { SET5(IsInvalidate, NeedsExclusive, IsUpgrade, IsRequest, NeedsResponse), 110 UpgradeResp, "UpgradeReq" }, 111 /* SCUpgradeReq: response could be UpgradeResp or UpgradeFailResp */ 112 { SET6(IsInvalidate, NeedsExclusive, IsUpgrade, IsLlsc, 113 IsRequest, NeedsResponse), 114 UpgradeResp, "SCUpgradeReq" }, 115 /* UpgradeResp */ 116 { SET3(NeedsExclusive, IsUpgrade, IsResponse), 117 InvalidCmd, "UpgradeResp" }, 118 /* SCUpgradeFailReq: generates UpgradeFailResp ASAP */ 119 { SET5(IsInvalidate, NeedsExclusive, IsLlsc, 120 IsRequest, NeedsResponse), 121 UpgradeFailResp, "SCUpgradeFailReq" }, 122 /* UpgradeFailResp */ 123 { SET2(NeedsExclusive, IsResponse), 124 InvalidCmd, "UpgradeFailResp" }, 125 /* ReadExReq */ 126 { SET5(IsRead, NeedsExclusive, IsInvalidate, IsRequest, NeedsResponse), 127 ReadExResp, "ReadExReq" }, 128 /* ReadExResp */ 129 { SET4(IsRead, NeedsExclusive, IsResponse, HasData), 130 InvalidCmd, "ReadExResp" }, 131 /* LoadLockedReq: note that we use plain ReadResp as response, so that 132 * we can also use ReadRespWithInvalidate when needed */ 133 { SET4(IsRead, IsLlsc, IsRequest, NeedsResponse), 134 ReadResp, "LoadLockedReq" }, 135 /* StoreCondReq */ 136 { SET6(IsWrite, NeedsExclusive, IsLlsc, 137 IsRequest, NeedsResponse, HasData), 138 StoreCondResp, "StoreCondReq" }, 139 /* StoreCondFailReq: generates failing StoreCondResp ASAP */ 140 { SET6(IsWrite, NeedsExclusive, IsLlsc, 141 IsRequest, NeedsResponse, HasData), 142 StoreCondResp, "StoreCondFailReq" }, 143 /* StoreCondResp */ 144 { SET4(IsWrite, NeedsExclusive, IsLlsc, IsResponse), 145 InvalidCmd, "StoreCondResp" }, 146 /* SwapReq -- for Swap ldstub type operations */ 147 { SET6(IsRead, IsWrite, NeedsExclusive, IsRequest, HasData, NeedsResponse), 148 SwapResp, "SwapReq" }, 149 /* SwapResp -- for Swap ldstub type operations */ 150 { SET5(IsRead, IsWrite, NeedsExclusive, IsResponse, HasData), 151 InvalidCmd, "SwapResp" }, 152 /* IntReq -- for interrupts */ 153 { SET4(IsWrite, IsRequest, NeedsResponse, HasData), 154 MessageResp, "MessageReq" }, 155 /* IntResp -- for interrupts */ 156 { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" }, 157 /* InvalidDestError -- packet dest field invalid */ 158 { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" }, 159 /* BadAddressError -- memory address invalid */ 160 { SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" }, 161 /* FunctionalReadError */ 162 { SET3(IsRead, IsResponse, IsError), InvalidCmd, "FunctionalReadError" }, 163 /* FunctionalWriteError */ 164 { SET3(IsWrite, IsResponse, IsError), InvalidCmd, "FunctionalWriteError" }, 165 /* PrintReq */ 166 { SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" }, 167 /* Flush Request */ 168 { SET3(IsRequest, IsFlush, NeedsExclusive), InvalidCmd, "FlushReq" }, 169 /* Invalidation Request */ 170 { SET3(NeedsExclusive, IsInvalidate, IsRequest), 171 InvalidCmd, "InvalidationReq" }, 172}; 173 174bool
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