1/*
2 * Copyright (c) 2011-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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179 { SET4(IsWrite, IsRequest, NeedsResponse, HasData),
180 MessageResp, "MessageReq" },
181 /* IntResp -- for interrupts */
182 { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" },
183 /* MemFenceReq -- for synchronization requests */
184 {SET2(IsRequest, NeedsResponse), MemFenceResp, "MemFenceReq"},
185 /* MemFenceResp -- for synchronization responses */
186 {SET1(IsResponse), InvalidCmd, "MemFenceResp"},
187 /* InvalidDestError -- packet dest field invalid */
188 { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" },
189 /* BadAddressError -- memory address invalid */
190 { SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" },
191 /* FunctionalReadError */
192 { SET3(IsRead, IsResponse, IsError), InvalidCmd, "FunctionalReadError" },
193 /* FunctionalWriteError */
194 { SET3(IsWrite, IsResponse, IsError), InvalidCmd, "FunctionalWriteError" },

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