mem_object.hh (8710:aab813d6a162) mem_object.hh (8922:17f037ad8918)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Andreas Hansson
29 */
30
31/**
32 * @file
42 */
43
44/**
45 * @file
33 * Base Memory Object declaration.
46 * MemObject declaration.
34 */
35
36#ifndef __MEM_MEM_OBJECT_HH__
37#define __MEM_MEM_OBJECT_HH__
38
39#include "mem/port.hh"
40#include "params/MemObject.hh"
41#include "sim/sim_object.hh"
42
43/**
47 */
48
49#ifndef __MEM_MEM_OBJECT_HH__
50#define __MEM_MEM_OBJECT_HH__
51
52#include "mem/port.hh"
53#include "params/MemObject.hh"
54#include "sim/sim_object.hh"
55
56/**
44 * The base MemoryObject class, allows for an accesor function to a
45 * simobj that returns the Port.
57 * The MemObject class extends the SimObject with accessor functions
58 * to get its master and slave ports.
46 */
47class MemObject : public SimObject
48{
49 public:
50 typedef MemObjectParams Params;
51 const Params *params() const
52 { return dynamic_cast<const Params *>(_params); }
53
54 MemObject(const Params *params);
55
59 */
60class MemObject : public SimObject
61{
62 public:
63 typedef MemObjectParams Params;
64 const Params *params() const
65 { return dynamic_cast<const Params *>(_params); }
66
67 MemObject(const Params *params);
68
56 public:
57 /** Additional function to return the Port of a memory object. */
58 virtual Port *getPort(const std::string &if_name, int idx = -1) = 0;
69 /**
70 * Get a master port with a given name and index.
71 *
72 * @param if_name Port name
73 * @param idx Index in the case of a VectorPort
74 *
75 * @return A reference to the given port
76 */
77 virtual MasterPort& getMasterPort(const std::string& if_name,
78 int idx = -1);
79
80 /**
81 * Get a slave port with a given name and index.
82 *
83 * @param if_name Port name
84 * @param idx Index in the case of a VectorPort
85 *
86 * @return A reference to the given port
87 */
88 virtual SlavePort& getSlavePort(const std::string& if_name,
89 int idx = -1);
59};
60
61#endif //__MEM_MEM_OBJECT_HH__
90};
91
92#endif //__MEM_MEM_OBJECT_HH__