1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * MemObject declaration.
47 */
48
49#ifndef __MEM_MEM_OBJECT_HH__
50#define __MEM_MEM_OBJECT_HH__
51
52#include "mem/port.hh"
53#include "params/MemObject.hh"
54#include "sim/clocked_object.hh"
55
56/**
57 * The MemObject class extends the ClockedObject with accessor functions
58 * to get its master and slave ports.
59 */
60class MemObject : public ClockedObject
61{
62 public:
63 typedef MemObjectParams Params;
64 const Params *params() const
65 { return dynamic_cast<const Params *>(_params); }
66
67 MemObject(const Params *params);
68
69 /**
70 * Get a master port with a given name and index. This is used at
71 * binding time and returns a reference to a protocol-agnostic
72 * base master port.
73 *
74 * @param if_name Port name
75 * @param idx Index in the case of a VectorPort
76 *
77 * @return A reference to the given port
78 */
79 virtual BaseMasterPort& getMasterPort(const std::string& if_name,
80 PortID idx = InvalidPortID);
81
82 /**
83 * Get a slave port with a given name and index. This is used at
84 * binding time and returns a reference to a protocol-agnostic
85 * base master port.
86 *
87 * @param if_name Port name
88 * @param idx Index in the case of a VectorPort
89 *
90 * @return A reference to the given port
91 */
92 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
93 PortID idx = InvalidPortID);
94};
95
96#endif //__MEM_MEM_OBJECT_HH__