mem_delay.hh (12823:ba630bc7a36d) mem_delay.hh (13784:1941dc118243)
1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64class MemDelay : public MemObject
65{
66
67 public:
68 MemDelay(const MemDelayParams *params);
69
70 void init() override;
71
1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 55 unchanged lines hidden (view full) ---

64class MemDelay : public MemObject
65{
66
67 public:
68 MemDelay(const MemDelayParams *params);
69
70 void init() override;
71
72 protected: // Port interfaces
73 BaseMasterPort& getMasterPort(const std::string &if_name,
74 PortID idx = InvalidPortID) override;
72 protected: // Port interface
73 Port &getPort(const std::string &if_name,
74 PortID idx=InvalidPortID) override;
75
75
76 BaseSlavePort& getSlavePort(const std::string &if_name,
77 PortID idx = InvalidPortID) override;
78
79 class MasterPort : public QueuedMasterPort
80 {
81 public:
82 MasterPort(const std::string &_name, MemDelay &_parent);
83
84 protected:
85 bool recvTimingResp(PacketPtr pkt) override;
86

--- 99 unchanged lines hidden --- 		76 class MasterPort : public QueuedMasterPort
77 {
78 public:
79 MasterPort(const std::string &_name, MemDelay &_parent);
80
81 protected:
82 bool recvTimingResp(PacketPtr pkt) override;
83

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