1/* 2 * Copyright (c) 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andreas Sandberg 38 */ 39 40#ifndef __MEM_MEM_DELAY_HH__ 41#define __MEM_MEM_DELAY_HH__ 42 43#include "mem/mem_object.hh" 44#include "mem/qport.hh" 45 46struct MemDelayParams; 47struct SimpleMemDelayParams; 48 49/** 50 * This abstract component provides a mechanism to delay 51 * packets. It can be spliced between arbitrary ports of the memory 52 * system and delays packets that pass through it. 53 * 54 * Specialisations of this abstract class should override at least one 55 * of delayReq, delayResp, deleySnoopReq, delaySnoopResp. These 56 * methods receive a PacketPtr as their argument and return a delay in 57 * Ticks. The base class implements an infinite buffer to hold delayed 58 * packets until they are ready. The intention is to use this 59 * component for rapid prototyping of other memory system components 60 * that introduce a packet processing delays. 61 * 62 * NOTE: Packets may be reordered if the delays aren't constant. 63 */ 64class MemDelay : public MemObject 65{ 66 67 public: 68 MemDelay(const MemDelayParams *params); 69 70 void init() override; 71 72 protected: // Port interfaces 73 BaseMasterPort& getMasterPort(const std::string &if_name, 74 PortID idx = InvalidPortID) override; 75 76 BaseSlavePort& getSlavePort(const std::string &if_name, 77 PortID idx = InvalidPortID) override; 78 79 class MasterPort : public QueuedMasterPort 80 { 81 public: 82 MasterPort(const std::string &_name, MemDelay &_parent); 83 84 protected: 85 bool recvTimingResp(PacketPtr pkt) override; 86 87 void recvFunctionalSnoop(PacketPtr pkt) override; 88 89 Tick recvAtomicSnoop(PacketPtr pkt) override; 90 91 void recvTimingSnoopReq(PacketPtr pkt) override; 92 93 void recvRangeChange() override { 94 parent.slavePort.sendRangeChange(); 95 } 96 97 bool isSnooping() const override { 98 return parent.slavePort.isSnooping(); 99 } 100 101 private: 102 MemDelay& parent; 103 }; 104 105 class SlavePort : public QueuedSlavePort 106 { 107 public: 108 SlavePort(const std::string &_name, MemDelay &_parent); 109 110 protected: 111 Tick recvAtomic(PacketPtr pkt) override; 112 bool recvTimingReq(PacketPtr pkt) override; 113 void recvFunctional(PacketPtr pkt) override; 114 bool recvTimingSnoopResp(PacketPtr pkt) override; 115 116 AddrRangeList getAddrRanges() const override { 117 return parent.masterPort.getAddrRanges(); 118 } 119 120 bool tryTiming(PacketPtr pkt) override { return true; } 121 122 private: 123 124 MemDelay& parent; 125 126 }; 127
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